Lines Matching +full:mdio +full:- +full:connected

8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
23 band back-pressure to the host CPU network interface when downstream interfaces
24 are connected at a lower speed.
27 contains a bunch of sub-blocks/registers:
29 - ``SWITCH_CORE``: common switch registers
30 - ``SWITCH_REG``: external interfaces switch register
31 - ``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE,
33 - ``SWITCH_INDIR_RW``: 64-bits wide register helper block
34 - ``SWITCH_INTRL2_0/1``: Level-2 interrupt controllers
35 - ``SWITCH_ACB``: Admission control block
36 - ``SWITCH_FCB``: Fail-over control block
45 The SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag
55 -------------------
66 MDIO indirect accesses
67 ----------------------
70 Broadcom switches connected to a SF2 require the use of the DSA slave MDIO bus
71 in order to properly configure them. By default, the SF2 pseudo-PHY address, and
72 an external switch pseudo-PHY address will both be snooping for incoming MDIO
74 "double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we
76 pseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a
77 configurable pseudo-PHY address which circumvents the initial design limitation.
80 -----------------------------------------
84 hardware contains logic which will assert/de-assert link states accordingly for
95 ----------------
100 - turning off internal buffers/memories
101 - disabling packet processing logic
102 - putting integrated PHYs in IDDQ/low-power
103 - reducing the switch core clock based on the active port count
104 - enabling and advertising EEE
105 - turning off RGMII data processing logic when the link goes down
107 Wake-on-LAN
108 -----------
110 Wake-on-LAN is currently implemented by utilizing the host processor Ethernet
111 MAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection
114 system-wide suspend/resume, only ports not participating in Wake-on-LAN are