Lines Matching full:dependency
55 - Address-dependency barriers (historical).
190 There is an obvious address dependency here, as the value loaded into D depends
395 address-dependency barriers; see the "SMP barrier pairing" subsection.
398 (2) Address-dependency barriers (historical).
400 An address-dependency barrier is a weaker form of read barrier. In the
403 the second load will be directed), an address-dependency barrier would
407 An address-dependency barrier is a partial ordering on interdependent
413 considered can then perceive. An address-dependency barrier issued by
418 the address-dependency barrier.
423 [!] Note that the first load really has to have an _address_ dependency and
424 not a control dependency. If the address for the second load is dependent
425 on the first load, but the dependency is through a conditional rather than
426 actually loading the address itself, then it's a _control_ dependency and
430 [!] Note that address-dependency barriers should normally be paired with
434 dependency barriers. Nowadays, APIs for marking loads from shared
436 address-dependency barriers.
440 A read barrier is an address-dependency barrier plus a guarantee that all
448 Read memory barriers imply address-dependency barriers, and so can
557 ADDRESS-DEPENDENCY BARRIERS (HISTORICAL)
565 address-dependency barriers.
568 load-to-store relations, address-dependency barriers are not necessary
571 The requirement of address-dependency barriers is a little subtle, and
585 doesn't imply an address-dependency barrier.
587 There's a clear address dependency here, and it would seem that by the end of
602 To deal with this, READ_ONCE() provides an implicit address-dependency barrier
612 <implicit address-dependency barrier>
629 An address-dependency barrier is not required to order dependent writes
646 Therefore, no address-dependency barrier is required to order the read into
648 even without an implicit address-dependency barrier of modern READ_ONCE():
653 of dependency ordering is to -prevent- writes to the data structure, along
659 Note well that the ordering provided by an address dependency is local to
664 The address-dependency barrier is very important to the RCU system,
680 A load-load control dependency requires a full read memory barrier, not
681 simply an (implicit) address-dependency barrier to make it work correctly.
685 <implicit address-dependency barrier>
687 /* BUG: No address dependency!!! */
692 dependency, but rather a control dependency that the CPU may short-circuit
838 defeating control dependency:
874 A weakly ordered CPU would have no dependency of any sort between the load
882 Note well that the ordering provided by a control dependency is local
902 destroy the control dependency while respecting the letter of the
913 dependency into nonexistence. Careful use of READ_ONCE() or
914 atomic{,64}_read() can help to preserve your control dependency.
918 of the if-statement containing the control dependency, including
921 control dependency.
942 with an address-dependency barrier, a control dependency, an acquire barrier,
944 read barrier, control dependency, or an address-dependency barrier pairs
963 <implicit address-dependency barrier>
973 <implicit control dependency>
983 match the loads after the read barrier or the address-dependency barrier, and
1036 Secondly, address-dependency barriers act as partial orderings on address-
1082 If, however, an address-dependency barrier were to be placed between the load
1093 <address-dependency barrier>
1307 Placing a read barrier or an address-dependency barrier just before the second
1409 only the data dependency shown below:
1415 <data dependency> <read barrier>
1422 The key point is that although CPU 2's data dependency orders its load
1838 ADDRESS DEPENDENCY READ_ONCE()
1841 All memory barriers except the address-dependency barriers imply a compiler
2455 CPU, that CPU's dependency ordering logic will take care of everything else.
2905 the address-dependency barrier really becomes necessary as this synchronises