Lines Matching refs:DMA
5 hardware (DMA) access across multiple device drivers and subsystems, and
17 Shared DMA Buffers
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
85 - Memory mapping the contents of the DMA buffer is also supported. See the
86 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
88 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
91 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
92 `DMA Buffer ioctls`_ below for details.
94 Basic Operation and Device DMA Access
100 CPU Access to DMA Buffer Objects
112 DMA-BUF statistics
117 DMA Buffer ioctls
122 DMA-BUF locking convention
149 DMA Fences
153 :doc: DMA fences overview
155 DMA Fence Cross-Driver Contract
161 DMA Fence Signalling Annotations
167 DMA Fence Deadline Hints
173 DMA Fences Functions Reference
182 DMA Fence Array
191 DMA Fence Chain
200 DMA Fence unwrap
206 DMA Fence Sync File
215 DMA Fence Sync File uABI
221 Indefinite DMA Fences
236 are then imported as a DMA fence for integration into existing winsys
240 batch DMA fences for memory management instead of context preemption DMA
245 in-kernel DMA fences does not work, even when a fallback timeout is included to
248 * Only the kernel knows about all DMA fence dependencies, userspace is not aware
256 dependent upon DMA fences. If the kernel also support indefinite fences in the
257 kernel like a DMA fence, like any of the above proposal would, there is the
266 kernel [label="Kernel DMA Fences"]
284 * No future fences, proxy fences or userspace fences imported as DMA fences,
287 * No DMA fences that signal end of batchbuffer for command submission where
296 implications for DMA fences.
300 But memory allocations are not allowed to gate completion of DMA fences, which
301 means any workload using recoverable page faults cannot use DMA fences for
306 Linux rely on DMA fences, which means without an entirely new userspace stack
315 job with a DMA fence and a compute workload using recoverable page faults are
322 allocation is waiting for the DMA fence of the 3D workload to complete.
330 - DMA fence workloads and workloads which need page fault handling have
333 reservations for DMA fence workloads.
336 hardware resources for DMA fence workloads when they are in-flight. This must
337 cover the time from when the DMA fence is visible to other threads up to
342 requiring DMA fences or jobs requiring page fault handling: This means all DMA
344 inserted into the scheduler queue. And vice versa, before a DMA fence can be
350 memory blocks or runtime tracking of the full dependency graph of all DMA
357 GPUs do not have any impact. This allows us to keep using DMA fences internally
361 In some ways this page fault problem is a special case of the `Infinite DMA
363 depend on DMA fences, but not the other way around. And not even the page fault