Lines Matching +full:inter +full:- +full:processor

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Palmer Dabbelt <palmer@dabbelt.com>
11   - Anup Patel <anup.patel@wdc.com>
14   SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15   Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16   interrupts. It directly connects to the timer and inter-processor interrupt
17   lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19   The clock frequency of CLINT is specified via "timebase-frequency" DT
20   property of "/cpus" DT node. The "timebase-frequency" DT property is
23   T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24   their implementation lacks a memory-mapped MTIME register, thus not
30       - items:
31           - enum:
32               - canaan,k210-clint       # Canaan Kendryte K210
33               - sifive,fu540-c000-clint # SiFive FU540
34               - starfive,jh7100-clint   # StarFive JH7100
35               - starfive,jh7110-clint   # StarFive JH7110
36           - const: sifive,clint0        # SiFive CLINT v0 IP block
37       - items:
38           - enum:
39               - allwinner,sun20i-d1-clint
40               - thead,th1520-clint
41           - const: thead,c900-clint
42       - items:
43           - const: sifive,clint0
44           - const: riscv,clint0
49       Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
51       sifive-blocks-ip-versioning.txt for details regarding the latter.
56   interrupts-extended:
63   - compatible
64   - reg
65   - interrupts-extended
68   - |
70       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
71       interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,