Lines Matching +full:exynos5433 +full:- +full:uart
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - items:
22 - const: samsung,exynosautov9-uart
23 - const: samsung,exynos850-uart
24 - enum:
25 - apple,s5l-uart
26 - axis,artpec8-uart
27 - samsung,s3c2410-uart
28 - samsung,s3c2412-uart
29 - samsung,s3c2440-uart
30 - samsung,s3c6400-uart
31 - samsung,s5pv210-uart
32 - samsung,exynos4210-uart
33 - samsung,exynos5433-uart
34 - samsung,exynos850-uart
39 reg-io-width:
49 clock-names:
53 - const: uart
54 - pattern: '^clk_uart_baud[0-3]$'
55 - pattern: '^clk_uart_baud[0-3]$'
56 - pattern: '^clk_uart_baud[0-3]$'
57 - pattern: '^clk_uart_baud[0-3]$'
61 - description: DMA controller phandle and request line for RX
62 - description: DMA controller phandle and request line for TX
64 dma-names:
66 - const: rx
67 - const: tx
74 power-domains:
77 samsung,uart-fifosize:
78 description: The fifo size supported by the UART channel.
83 - compatible
84 - clocks
85 - clock-names
86 - interrupts
87 - reg
92 - $ref: serial.yaml#
94 - if:
99 - samsung,s3c2410-uart
100 - samsung,s5pv210-uart
106 clock-names:
109 - const: uart
110 - pattern: '^clk_uart_baud[0-1]$'
111 - pattern: '^clk_uart_baud[0-1]$'
113 - if:
118 - apple,s5l-uart
119 - axis,artpec8-uart
120 - samsung,exynos4210-uart
121 - samsung,exynos5433-uart
126 clock-names:
128 - const: uart
129 - const: clk_uart_baud0
132 - |
133 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
136 compatible = "samsung,s3c6400-uart";
138 interrupt-parent = <&vic1>;
140 clock-names = "uart", "clk_uart_baud2",
144 samsung,uart-fifosize = <16>;