Lines Matching +full:riscv +full:- +full:isa +full:- +full:manual
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
31 const: riscv
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
39 https://riscv.org/specifications/
41 Due to revisions of the ISA specification, some deviations
43 Notably, riscv,isa was defined prior to the creation of the
47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
54 riscv,isa-base:
56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specification.
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
69 - const: i
72 version of the unprivileged ISA specification.
78 - const: m
81 ratified in the 20191213 version of the unprivileged ISA
84 - const: a
87 20191213 version of the unprivileged ISA specification.
89 - const: f
91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version of the unprivileged ISA
95 - const: d
97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version of the unprivileged ISA
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version of the unprivileged ISA
107 - const: c
110 the 20191213 version of the unprivileged ISA specification.
112 - const: v
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
121 version of the privileged ISA specification.
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: ssaia
133 The standard Ssaia supervisor-level extension for the advanced
134 interrupt architecture for supervisor-mode-visible csr and
136 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
138 - const: sscofpmf
140 The standard Sscofpmf supervisor-level extension for count overflow
141 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
142 to manually trigger workflow. (#2)") of riscv-count-overflow.
144 - const: sstc
146 The standard Sstc supervisor-level extension for time compare as
148 workflow. (#2)") of riscv-time-compare.
150 - const: svinval
152 The standard Svinval supervisor-level extension for fine-grained
153 address-translation cache invalidation as ratified in the 20191213
154 version of the privileged ISA specification.
156 - const: svnapot
158 The standard Svnapot supervisor-level extensions for napot
160 privileged ISA specification.
162 - const: svpbmt
164 The standard Svpbmt supervisor-level extensions for page-based
166 ISA specification.
168 - const: zba
170 The standard Zba bit-manipulation extension for address generation
172 request #158 from hirooih/clmul-fix-loop-end-condition") of
173 riscv-bitmanip.
175 - const: zbb
177 The standard Zbb bit-manipulation extension for basic bit-manipulation
179 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
181 - const: zbc
183 The standard Zbc bit-manipulation extension for carry-less
185 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
187 - const: zbs
189 The standard Zbs bit-manipulation extension for single-bit
191 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
193 - const: zicbom
196 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
198 - const: zicbop
200 The standard Zicbop extension for cache-block prefetch instructions
201 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
202 riscv-CMOs.
204 - const: zicboz
206 The standard Zicboz extension for cache-block zeroing as ratified
207 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
209 - const: zicntr
212 ratified in the 20191213 version of the unprivileged ISA
215 - const: zicsr
219 unprivileged ISA specification.
222 special case read-only CSRs, that were moved into the Zicntr and
226 - const: zifencei
228 The standard Zifencei extension for instruction-fetch fence, as
229 ratified in the 20191213 version of the unprivileged ISA
232 - const: zihintpause
235 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
237 - const: zihpm
240 ratified in the 20191213 version of the unprivileged ISA
243 - const: ztso
247 riscv-isa-manual.