Lines Matching +full:versal +full:- +full:cpm +full:- +full:host +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
24 - description: Configuration space region and bridge registers.
25 - description: CPM5 control and status registers.
28 reg-names:
30 - const: cpm_slcr
31 - const: cfg
32 - const: cpm_csr
36 maxItems: 1
38 msi-map:
45 "#interrupt-cells":
46 const: 1
48 interrupt-controller:
52 "#address-cells":
54 "#interrupt-cells":
55 const: 1
56 "interrupt-controller": true
60 - reg
61 - reg-names
62 - "#interrupt-cells"
63 - interrupts
64 - interrupt-map
65 - interrupt-map-mask
66 - bus-range
67 - msi-map
68 - interrupt-controller
73 - |
75 versal {
76 #address-cells = <2>;
77 #size-cells = <2>;
79 compatible = "xlnx,versal-cpm-host-1.00";
81 #address-cells = <3>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
85 interrupt-parent = <&gic>;
86 interrupt-map-mask = <0 0 0 7>;
87 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
88 <0 0 0 2 &pcie_intc_0 1>,
91 bus-range = <0x00 0xff>;
94 msi-map = <0x0 &its_gic 0x0 0x10000>;
97 reg-names = "cpm_slcr", "cfg";
98 pcie_intc_0: interrupt-controller {
99 #address-cells = <0>;
100 #interrupt-cells = <1>;
101 interrupt-controller;
106 compatible = "xlnx,versal-cpm5-host";
108 #address-cells = <3>;
109 #interrupt-cells = <1>;
110 #size-cells = <2>;
112 interrupt-parent = <&gic>;
113 interrupt-map-mask = <0 0 0 7>;
114 interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
115 <0 0 0 2 &pcie_intc_1 1>,
118 bus-range = <0x00 0xff>;
121 msi-map = <0x0 &its_gic 0x0 0x10000>;
125 reg-names = "cpm_slcr", "cfg", "cpm_csr";
127 pcie_intc_1: interrupt-controller {
128 #address-cells = <0>;
129 #interrupt-cells = <1>;
130 interrupt-controller;