Lines Matching +full:ecam +full:- +full:based
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
27 - nvidia,tegra234-pcie
32 - description: controller's application logic registers
33 - description: configuration registers
34 - description: iATU and DMA registers. This is where the iATU (internal
37 - description: aperture where the Root Port's own configuration
39 - description: aperture to access the configuration space through ECAM.
41 reg-names:
44 - const: appl
45 - const: config
46 - const: atu_dma
47 - const: dbi
48 - const: ecam
52 - description: controller interrupt
53 - description: MSI interrupt
55 interrupt-names:
57 - const: intr
58 - const: msi
62 - description: module clock
64 clock-names:
66 - const: core
70 - description: APB bus interface reset
71 - description: module reset
73 reset-names:
75 - const: apb
76 - const: core
82 phy-names:
85 - const: p2u-0
86 - const: p2u-1
87 - const: p2u-2
88 - const: p2u-3
89 - const: p2u-4
90 - const: p2u-5
91 - const: p2u-6
92 - const: p2u-7
94 power-domains:
100 Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
101 Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
105 - description: memory read client
106 - description: memory write client
108 interconnect-names:
110 - const: dma-mem # read
111 - const: write
113 dma-coherent: true
116 $ref: /schemas/types.yaml#/definitions/phandle-array
145 - items:
146 - description: phandle to BPMP controller node
147 - description: PCIe controller ID
150 nvidia,update-fc-fixup:
161 a) speed is Gen-2 and MPS is 256B
162 b) speed is >= Gen-3 with any MPS
166 nvidia,aspm-cmrt-us:
170 nvidia,aspm-pwr-on-t-us:
174 nvidia,aspm-l0s-entrance-latency-us:
177 vddio-pex-ctl-supply:
180 vpcie3v3-supply:
183 in p2972-0000 platform.
185 vpcie12v-supply:
188 in p2972-0000 platform.
190 nvidia,enable-srns:
194 Spread-Spectrum Clocking). NOTE: This is applicable only for
199 nvidia,enable-ext-refclk:
208 - $ref: /schemas/pci/snps,dw-pcie.yaml#
209 - if:
214 - nvidia,tegra194-pcie
219 reg-names:
222 - if:
227 - nvidia,tegra234-pcie
232 reg-names:
238 - interrupts
239 - interrupt-names
240 - interrupt-map
241 - interrupt-map-mask
242 - clocks
243 - clock-names
244 - resets
245 - reset-names
246 - power-domains
247 - vddio-pex-ctl-supply
248 - num-lanes
249 - phys
250 - phy-names
251 - nvidia,bpmp
254 - |
255 #include <dt-bindings/clock/tegra194-clock.h>
256 #include <dt-bindings/interrupt-controller/arm-gic.h>
257 #include <dt-bindings/power/tegra194-powergate.h>
258 #include <dt-bindings/reset/tegra194-reset.h>
261 #address-cells = <2>;
262 #size-cells = <2>;
266 compatible = "nvidia,tegra194-pcie";
267 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
272 reg-names = "appl", "config", "atu_dma", "dbi";
274 #address-cells = <3>;
275 #size-cells = <2>;
277 num-lanes = <8>;
278 linux,pci-domain = <0>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
284 clock-names = "core";
288 reset-names = "apb", "core";
292 interrupt-names = "intr", "msi";
294 #interrupt-cells = <1>;
295 interrupt-map-mask = <0 0 0 0>;
296 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
300 supports-clkreq;
301 nvidia,aspm-cmrt-us = <60>;
302 nvidia,aspm-pwr-on-t-us = <20>;
303 nvidia,aspm-l0s-entrance-latency-us = <3>;
305 bus-range = <0x0 0xff>;
307 … <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
310 vddio-pex-ctl-supply = <&vdd_1v8ao>;
311 vpcie3v3-supply = <&vdd_3v3_pcie>;
312 vpcie12v-supply = <&vdd_12v_pcie>;
316 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
320 - |
321 #include <dt-bindings/clock/tegra234-clock.h>
322 #include <dt-bindings/interrupt-controller/arm-gic.h>
323 #include <dt-bindings/power/tegra234-powergate.h>
324 #include <dt-bindings/reset/tegra234-reset.h>
327 #address-cells = <2>;
328 #size-cells = <2>;
332 compatible = "nvidia,tegra234-pcie";
333 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
338 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
339 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
341 #address-cells = <3>;
342 #size-cells = <2>;
344 num-lanes = <4>;
345 num-viewport = <8>;
346 linux,pci-domain = <4>;
349 clock-names = "core";
353 reset-names = "apb", "core";
357 interrupt-names = "intr", "msi";
359 #interrupt-cells = <1>;
360 interrupt-map-mask = <0 0 0 0>;
361 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
365 nvidia,aspm-cmrt-us = <60>;
366 nvidia,aspm-pwr-on-t-us = <20>;
367 nvidia,aspm-l0s-entrance-latency-us = <3>;
369 bus-range = <0x0 0xff>;
371 … <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
374 vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
378 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";