Lines Matching +full:mdio +full:- +full:connected
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
19 - $ref: /schemas/net/mdio-mux.yaml#
24 - const: mdio-mux-mmioreg
25 - const: mdio-mux
33 mux-mask:
35 description: Contains an eight-bit mask that specifies which bits in the
37 child mdio-mux node must be constrained by this mask.
40 - compatible
41 - reg
42 - mux-mask
47 - |
48 mdio-mux@9 {
49 compatible = "mdio-mux-mmioreg", "mdio-mux";
50 mdio-parent-bus = <&xmdio0>;
51 #address-cells = <1>;
52 #size-cells = <0>;
54 mux-mask = <0x6>; // EMI2
56 mdio@0 { // Slot 1 XAUI (FM2)
58 #address-cells = <1>;
59 #size-cells = <0>;
61 phy_xgmii_slot1: ethernet-phy@4 {
62 compatible = "ethernet-phy-ieee802.3-c45";
67 mdio@2 { // Slot 2 XAUI (FM1)
69 #address-cells = <1>;
70 #size-cells = <0>;
72 ethernet-phy@4 {
73 compatible = "ethernet-phy-ieee802.3-c45";