Lines Matching +full:switch +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros QCA83xx switch family
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
29 - qca,qca8328
30 - qca,qca8334
31 - qca,qca8337
33 qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
34 qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
35 qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
36 qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
41 reset-gpios:
46 qca,ignore-power-on-sel:
49 Ignore power-on pin strapping to configure LED open-drain or EEPROM
53 qca,led-open-drain:
56 Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
58 OEM does not use pin strapping to set this mode and prefers to set it
59 using SW regs. The pin strappings related to LED open-drain mode are
65 description: Qca8k switch have an internal mdio to access switch port.
69 mdio is the switch reg with an offset of -1.
74 "^(ethernet-)?ports$":
77 "^(ethernet-)?port@[0-6]$":
79 description: Ethernet switch ports
81 $ref: dsa-port.yaml#
84 qca,sgmii-rxclk-falling-edge:
90 qca,sgmii-txclk-falling-edge:
95 qca,sgmii-enable-pll:
108 - required:
109 - ports
110 - required:
111 - ethernet-ports
114 - compatible
115 - reg
120 - |
121 #include <dt-bindings/gpio/gpio.h>
122 #include <dt-bindings/leds/common.h>
125 #address-cells = <1>;
126 #size-cells = <0>;
128 external_phy_port1: ethernet-phy@0 {
132 external_phy_port2: ethernet-phy@1 {
136 external_phy_port3: ethernet-phy@2 {
140 external_phy_port4: ethernet-phy@3 {
144 external_phy_port5: ethernet-phy@4 {
148 switch@10 {
150 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
154 #address-cells = <1>;
155 #size-cells = <0>;
160 phy-mode = "rgmii";
162 fixed-link {
164 full-duplex;
171 phy-handle = <&external_phy_port1>;
177 phy-handle = <&external_phy_port2>;
183 phy-handle = <&external_phy_port3>;
189 phy-handle = <&external_phy_port4>;
195 phy-handle = <&external_phy_port5>;
200 - |
201 #include <dt-bindings/gpio/gpio.h>
204 #address-cells = <1>;
205 #size-cells = <0>;
207 switch@10 {
209 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
213 #address-cells = <1>;
214 #size-cells = <0>;
219 phy-mode = "rgmii";
221 fixed-link {
223 full-duplex;
230 phy-mode = "internal";
231 phy-handle = <&internal_phy_port1>;
234 #address-cells = <1>;
235 #size-cells = <0>;
241 default-state = "keep";
248 default-state = "keep";
256 phy-mode = "internal";
257 phy-handle = <&internal_phy_port2>;
263 phy-mode = "internal";
264 phy-handle = <&internal_phy_port3>;
270 phy-mode = "internal";
271 phy-handle = <&internal_phy_port4>;
277 phy-mode = "internal";
278 phy-handle = <&internal_phy_port5>;
284 phy-mode = "sgmii";
286 qca,sgmii-rxclk-falling-edge;
288 fixed-link {
290 full-duplex;
296 #address-cells = <1>;
297 #size-cells = <0>;
299 internal_phy_port1: ethernet-phy@0 {
303 internal_phy_port2: ethernet-phy@1 {
307 internal_phy_port3: ethernet-phy@2 {
311 internal_phy_port4: ethernet-phy@3 {
315 internal_phy_port5: ethernet-phy@4 {