Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10   - Miquel Raynal <miquel.raynal@bootlin.com>
13   - $ref: nand-chip.yaml#
16   The ECC strength and ECC step size properties define the user
18   they request the ECC engine to correct {strength} bit errors per
19   {size} bytes for a particular raw NAND chip.
21   The interpretation of these parameters is implementation-defined, so
28     pattern: "^nand@[a-f0-9]$"
32       Contains the chip-select IDs.
34   nand-ecc-placement:
36       Location of the ECC bytes. This location is unknown by default
37       but can be explicitly set to "oob", if all ECC bytes are
38       known to be stored in the OOB area, or "interleaved" if ECC
44   nand-ecc-mode:
46       Legacy ECC configuration mixing the ECC engine choice and
49     enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]
52   nand-bus-width:
54       Bus width to the NAND chip
59   nand-on-flash-bbt:
64       it as the device ages. Otherwise, the out-of-band area of a
70   nand-ecc-maximize:
72       Whether or not the ECC strength should be maximized. The
73       maximum ECC strength is both controller and chip
74       dependent. The ECC engine has to select the ECC config
77       only the in-band area is used by the upper layers, and you
78       want to make your NAND as reliable as possible.
81   nand-is-boot-medium:
83       Whether or not the NAND chip is a boot medium. Drivers might
84       use this information to select ECC algorithms supported by
88   nand-rb:
91     $ref: /schemas/types.yaml#/definitions/uint32-array
93   rb-gpios:
97       Ready/Busy pins. Active state refers to the NAND ready state and
100   wp-gpios:
103       Active state refers to the NAND Write Protect state and should be
108   - reg