Lines Matching +full:nand +full:- +full:controller

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Controller Common Properties
10   - Miquel Raynal <miquel.raynal@bootlin.com>
11   - Richard Weinberger <richard@nod.at>
14   The NAND controller should be represented with its own DT node, and
15   all NAND chips attached to this controller should be defined as
16   children nodes of the NAND controller. This representation should be
21     pattern: "^nand-controller(@.*)?"
23   "#address-cells":
26   "#size-cells":
31   cs-gpios:
33       Array of chip-select available to the controller. The first
34       entries are a 1:1 mapping of the available chip-select on the
35       NAND controller (even if they are not used). As many additional
36       chip-select as needed may follow and should be phandles of GPIO
37       lines. 'reg' entries of the NAND chip subnodes become indexes of
43   "^nand@[a-f0-9]$":
45     $ref: raw-nand-chip.yaml#
48   - "#address-cells"
49   - "#size-cells"
55   - |
56     nand-controller {
57       #address-cells = <1>;
58       #size-cells = <0>;
59       cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
61       /* controller specific properties */
63       nand@0 {
65         /* NAND chip specific properties */
68       nand@1 {