Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
29 bits with which to control the 8 exposed NAND interrupts, as well as hardware
33 interesting ways, sometimes with registers that lump multiple NAND-related
37 register resources within the NAND controller node above.
42 - items:
43 - enum:
44 - brcm,brcmnand-v2.1
45 - brcm,brcmnand-v2.2
46 - brcm,brcmnand-v4.0
47 - brcm,brcmnand-v5.0
48 - brcm,brcmnand-v6.0
49 - brcm,brcmnand-v6.1
50 - brcm,brcmnand-v6.2
51 - brcm,brcmnand-v7.0
52 - brcm,brcmnand-v7.1
53 - brcm,brcmnand-v7.2
54 - brcm,brcmnand-v7.3
55 - const: brcm,brcmnand
56 - description: BCM63138 SoC-specific NAND controller
58 - const: brcm,nand-bcm63138
59 - enum:
60 - brcm,brcmnand-v7.0
61 - brcm,brcmnand-v7.1
62 - const: brcm,brcmnand
63 - description: iProc SoC-specific NAND controller
65 - const: brcm,nand-iproc
66 - const: brcm,brcmnand-v6.1
67 - const: brcm,brcmnand
68 - description: BCM63168 SoC-specific NAND controller
70 - const: brcm,nand-bcm63168
71 - const: brcm,nand-bcm6368
72 - const: brcm,brcmnand-v4.0
73 - const: brcm,brcmnand
79 reg-names:
83 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
88 - description: NAND CTLRDY interrupt
89 … - description: FLASH_DMA_DONE (if flash DMA is available) or FLASH_EDU_DONE (if EDU is available)
91 interrupt-names:
94 - const: nand_ctlrdy
95 - enum:
96 - flash_dma_done
97 - flash_edu_done
101 description: reference to the clock for the NAND controller
103 clock-names:
104 const: nand
106 brcm,nand-has-wp:
108 Some versions of this IP include a write-protect
115 "^nand@[a-f0-9]$":
117 $ref: raw-nand-chip.yaml
122 nand-ecc-step-size:
125 brcm,nand-oob-sector-size:
128 expected for the ECC layout in use. This size, in
129 addition to the strength and step-size,
130 determines how the hardware BCH engine will lay
133 the flash geometry (particularly the NAND page
135 from NAND, the boot controller has only a limited
136 number of available options for its default ECC
143 - $ref: nand-controller.yaml#
144 - if:
148 const: brcm,nand-bcm63138
151 reg-names:
153 - const: nand
154 - const: nand-int-base
155 - if:
159 const: brcm,nand-bcm6368
162 reg-names:
164 - const: nand
165 - const: nand-int-base
166 - const: nand-cache
167 - if:
171 const: brcm,nand-iproc
174 reg-names:
176 - const: nand
177 - const: iproc-idm
178 - const: iproc-ext
179 - if:
185 - interrupt-names
190 - reg
191 - reg-names
192 - interrupts
195 - |
196 nand-controller@f0442800 {
197 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
200 reg-names = "nand", "flash-dma";
201 interrupt-parent = <&hif_intr2_intc>;
203 interrupt-names = "nand_ctlrdy", "flash_dma_done";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 nand@1 {
211 nand-on-flash-bbt;
212 nand-ecc-strength = <12>;
213 nand-ecc-step-size = <512>;
215 #address-cells = <1>;
216 #size-cells = <1>;
219 - |
220 nand-controller@10000200 {
221 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
222 "brcm,brcmnand-v4.0", "brcm,brcmnand";
226 reg-names = "nand", "nand-int-base", "nand-cache";
227 interrupt-parent = <&periph_intc>;
230 clock-names = "nand";
232 #address-cells = <1>;
233 #size-cells = <0>;
235 nand@0 {
238 nand-on-flash-bbt;
239 nand-ecc-strength = <1>;
240 nand-ecc-step-size = <512>;
242 #address-cells = <1>;
243 #size-cells = <1>;