Lines Matching full:description

13 description:
25     description: Minimum clock period for synchronous mode
30     description: Assertion time
34     description: Read deassertion time
38     description: Write deassertion time
43     description: Assertion time
47     description: Read deassertion time
51     description: Write deassertion time
55     description: Assertion time for AAD
59     description: Read deassertion time for AAD
63     description: Write deassertion time for AAD
68     description: Assertion time
72     description: Deassertion time
77     description: Assertion time
81     description: Deassertion time
85     description: Assertion time for AAD
89     description: Deassertion time for AAD
95     description: Multiple access word delay
99     description: Start-cycle to first data valid delay
103     description: Total read cycle time
107     description: Total write cycle time
111     description: Turn-around time between successive accesses
115     description: Delay between chip-select pulses
119     description: GPMC clock activation time
123     description: Start of wait monitoring with regard to valid data
129     description: ADV signal is delayed by half GPMC clock
133     description: CS signal is delayed by half GPMC clock
137     description: |
143     description: |
149     description: OE signal is delayed by half GPMC clock
153     description: WE signal is delayed by half GPMC clock
157     description: Multiply all access times by 2
162     description: |
171     description: |
179     description: Page/burst length.
185     description: Enables wrap bursting
189     description: Enables read page/burst mode
193     description: Enables write page/burst mode
197     description: |
207     description: |
217     description: |
223     description: |
229     description: |
234     description: |
241     description: Enables wait monitoring on reads.
245     description: Enables wait monitoring on writes.