Lines Matching refs:VP
24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
36 - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
57 - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
80 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
82 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
84 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
86 /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
99 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
122 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
124 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
126 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
128 /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
141 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
164 /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
166 /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */