Lines Matching +full:three +full:- +full:level

1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
19 required to have a HLIC with these three interrupt sources present.  Since the
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>.  The interrupt sources are defined by the
29   RISC-V supervisor ISA manual, with only the following three interrupts being
31     - Source 1 is the supervisor software interrupt, which can be sent by an SBI
33     - Source 5 is the supervisor timer interrupt, which can be configured by
34       SBI calls and implements a one-shot timer.
35     - Source 9 is the supervisor external interrupt, which chains to all other
37 - interrupt-controller : Identifies the node as an interrupt controller
39 Furthermore, this interrupt-controller MUST be embedded inside the cpu
47 		cpu1-intc: interrupt-controller {
48 			#interrupt-cells = <1>;
49 			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
50 			interrupt-controller;