Lines Matching +full:fast +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
21 - description: Tegra20 has specific I2C controller called as DVC I2C
22 controller. This only support master mode of I2C communication.
25 compatible with "nvidia,tegra20-i2c-dvc".
26 const: nvidia,tegra20-i2c-dvc
27 - description: |
32 with "nvidia,tegra30-i2c" to enable the continue transfer support.
33 This is also compatible with "nvidia,tegra20-i2c" without continue
36 - const: nvidia,tegra30-i2c
37 - const: nvidia,tegra20-i2c
38 - description: |
41 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
42 and fast-clk. Tegra114 has only one clock source called as
43 div-clk and hence clock mechanism is changed in I2C controller.
44 - Tegra30/Tegra20 I2C controller has enabled per packet transfer
49 compatible with "nvidia,tegra114-i2c".
50 const: nvidia,tegra114-i2c
51 - description: |
55 const: nvidia,tegra124-i2c
56 - description: |
60 - const: nvidia,tegra210-i2c
61 - const: nvidia,tegra124-i2c
62 - description: |
64 the VE power domain and typically used for camera use-cases. This VI
69 mode.
70 const: nvidia,tegra210-i2c-vi
71 - description: |
73 (always-on) partition of the SoC. All of these controllers are very
75 const: nvidia,tegra186-i2c
76 - description: |
78 (always-on) partition of the SoC. All of these controllers are very
82 const: nvidia,tegra194-i2c
90 '#address-cells':
93 '#size-cells':
100 clock-names:
106 - description: module reset
108 reset-names:
110 - const: i2c
114 - description: DMA channel for the reception FIFO
115 - description: DMA channel for the transmission FIFO
117 dma-names:
119 - const: rx
120 - const: tx
123 - $ref: /schemas/i2c/i2c-controller.yaml
124 - if:
129 - nvidia,tegra20-i2c
130 - nvidia,tegra30-i2c
133 clock-names:
135 - const: div-clk
136 - const: fast-clk
138 - if:
142 const: nvidia,tegra114-i2c
145 clock-names:
147 - const: div-clk
149 - if:
153 const: nvidia,tegra210-i2c
156 clock-names:
158 - const: div-clk
160 - if:
164 const: nvidia,tegra210-i2c-vi
167 clock-names:
169 - const: div-clk
170 - const: slow
171 power-domains:
173 - description: phandle to the VENC power domain
178 - |
180 compatible = "nvidia,tegra20-i2c";
184 clock-names = "div-clk", "fast-clk";
186 reset-names = "i2c";
188 dma-names = "rx", "tx";
190 #address-cells = <1>;
191 #size-cells = <0>;