Lines Matching +full:error +full:- +full:correction

3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
4 correction check).
6 The memory controller supports SECDED (single bit error correction, double bit
7 error detection) and single bit error auto scrubbing by reserving 8 bits for
14 - compatible: should be one of
15 	- "aspeed,ast2400-sdram-edac"
16 	- "aspeed,ast2500-sdram-edac"
17 	- "aspeed,ast2600-sdram-edac"
18 - reg:        sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
25 		compatible = "aspeed,ast2500-sdram-edac";