Lines Matching +full:qcm2290 +full:- +full:bimc
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 are mentioned for QCM2290 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,qcm2290-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: bus
33 - const: core
41 interconnect-names:
45 "^display-controller@[0-9a-f]+$":
49 const: qcom,qcm2290-dpu
51 "^dsi@[0-9a-f]+$":
55 const: qcom,dsi-ctrl-6g-qcm2290
57 "^phy@[0-9a-f]+$":
61 const: qcom,dsi-phy-14nm-2290
64 - compatible
69 - |
70 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
71 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
72 #include <dt-bindings/clock/qcom,rpmcc.h>
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 #include <dt-bindings/interconnect/qcom,qcm2290.h>
75 #include <dt-bindings/power/qcom-rpmpd.h>
77 display-subsystem@5e00000 {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "qcom,qcm2290-mdss";
82 reg-names = "mdss";
83 power-domains = <&dispcc MDSS_GDSC>;
87 clock-names = "iface", "bus", "core";
90 interrupt-controller;
91 #interrupt-cells = <1>;
93 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
94 interconnect-names = "mdp0-mem";
100 display-controller@5e01000 {
101 compatible = "qcom,qcm2290-dpu";
104 reg-names = "mdp", "vbif";
111 clock-names = "bus", "iface", "core", "lut", "vsync";
113 operating-points-v2 = <&mdp_opp_table>;
114 power-domains = <&rpmpd QCM2290_VDDCX>;
116 interrupt-parent = <&mdss>;
120 #address-cells = <1>;
121 #size-cells = <0>;
126 remote-endpoint = <&dsi0_in>;
133 compatible = "qcom,dsi-ctrl-6g-qcm2290";
135 reg-names = "dsi_ctrl";
137 interrupt-parent = <&mdss>;
146 clock-names = "byte",
152 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
153 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
155 operating-points-v2 = <&dsi_opp_table>;
156 power-domains = <&rpmpd QCM2290_VDDCX>;
159 phy-names = "dsi";
161 #address-cells = <1>;
162 #size-cells = <0>;
165 #address-cells = <1>;
166 #size-cells = <0>;
171 remote-endpoint = <&dpu_intf1_out>;
184 compatible = "qcom,dsi-phy-14nm-2290";
188 reg-names = "dsi_phy",
192 #clock-cells = <1>;
193 #phy-cells = <0>;
196 clock-names = "iface", "ref";
197 vcca-supply = <&vreg_dsi_phy>;