Lines Matching +full:- +full:clock
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - linux-fsd@tesla.com
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
25 - tesla,fsd-clock-imem
26 - tesla,fsd-clock-peric
27 - tesla,fsd-clock-fsys0
28 - tesla,fsd-clock-fsys1
29 - tesla,fsd-clock-mfc
30 - tesla,fsd-clock-cam_csi
36 clock-names:
40 "#clock-cells":
47 - if:
51 const: tesla,fsd-clock-cmu
56 - description: External reference clock (24 MHz)
57 clock-names:
59 - const: fin_pll
61 - if:
65 const: tesla,fsd-clock-imem
70 - description: External reference clock (24 MHz)
71 - description: IMEM TCU clock (from CMU_CMU)
72 - description: IMEM bus clock (from CMU_CMU)
73 - description: IMEM DMA clock (from CMU_CMU)
74 clock-names:
76 - const: fin_pll
77 - const: dout_cmu_imem_tcuclk
78 - const: dout_cmu_imem_aclk
79 - const: dout_cmu_imem_dmaclk
81 - if:
85 const: tesla,fsd-clock-peric
90 - description: External reference clock (24 MHz)
91 - description: Shared0 PLL div4 clock (from CMU_CMU)
92 - description: PERIC shared1 div36 clock (from CMU_CMU)
93 - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
94 - description: PERIC shared0 div20 clock (from CMU_CMU)
95 - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
96 clock-names:
98 - const: fin_pll
99 - const: dout_cmu_pll_shared0_div4
100 - const: dout_cmu_peric_shared1div36
101 - const: dout_cmu_peric_shared0div3_tbuclk
102 - const: dout_cmu_peric_shared0div20
103 - const: dout_cmu_peric_shared1div4_dmaclk
105 - if:
109 const: tesla,fsd-clock-fsys0
114 - description: External reference clock (24 MHz)
115 - description: Shared0 PLL div6 clock (from CMU_CMU)
116 - description: FSYS0 shared1 div4 clock (from CMU_CMU)
117 - description: FSYS0 shared0 div4 clock (from CMU_CMU)
118 clock-names:
120 - const: fin_pll
121 - const: dout_cmu_pll_shared0_div6
122 - const: dout_cmu_fsys0_shared1div4
123 - const: dout_cmu_fsys0_shared0div4
125 - if:
129 const: tesla,fsd-clock-fsys1
134 - description: External reference clock (24 MHz)
135 - description: FSYS1 shared0 div8 clock (from CMU_CMU)
136 - description: FSYS1 shared0 div4 clock (from CMU_CMU)
137 clock-names:
139 - const: fin_pll
140 - const: dout_cmu_fsys1_shared0div8
141 - const: dout_cmu_fsys1_shared0div4
143 - if:
147 const: tesla,fsd-clock-mfc
152 - description: External reference clock (24 MHz)
153 clock-names:
155 - const: fin_pll
157 - if:
161 const: tesla,fsd-clock-cam_csi
166 - description: External reference clock (24 MHz)
167 clock-names:
169 - const: fin_pll
172 - compatible
173 - "#clock-cells"
174 - clocks
175 - clock-names
176 - reg
181 # Clock controller node for CMU_FSYS1
182 - |
183 #include <dt-bindings/clock/fsd-clk.h>
185 clock_fsys1: clock-controller@16810000 {
186 compatible = "tesla,fsd-clock-fsys1";
188 #clock-cells = <1>;
193 clock-names = "fin_pll",