Lines Matching +full:exynos7885 +full:- +full:cmu +full:- +full:peri
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7885 SoC clock controller
10 - Dávid Virág <virag.david003@gmail.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
17 Exynos7885 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
21 as a fixed-rate clock in dts.
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
29 'dt-bindings/clock/exynos7885.h' header.
34 - samsung,exynos7885-cmu-top
35 - samsung,exynos7885-cmu-core
36 - samsung,exynos7885-cmu-fsys
37 - samsung,exynos7885-cmu-peri
43 clock-names:
47 "#clock-cells":
54 - if:
58 const: samsung,exynos7885-cmu-top
64 - description: External reference clock (26 MHz)
66 clock-names:
68 - const: oscclk
70 - if:
74 const: samsung,exynos7885-cmu-core
80 - description: External reference clock (26 MHz)
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
85 clock-names:
87 - const: oscclk
88 - const: dout_core_bus
89 - const: dout_core_cci
90 - const: dout_core_g3d
92 - if:
96 const: samsung,exynos7885-cmu-fsys
102 - description: External reference clock (26 MHz)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
109 clock-names:
111 - const: oscclk
112 - const: dout_fsys_bus
113 - const: dout_fsys_mmc_card
114 - const: dout_fsys_mmc_embd
115 - const: dout_fsys_mmc_sdio
116 - const: dout_fsys_usb30drd
118 - if:
122 const: samsung,exynos7885-cmu-peri
128 - description: External reference clock (26 MHz)
129 - description: CMU_PERI bus clock (from CMU_TOP)
130 - description: SPI0 clock (from CMU_TOP)
131 - description: SPI1 clock (from CMU_TOP)
132 - description: UART0 clock (from CMU_TOP)
133 - description: UART1 clock (from CMU_TOP)
134 - description: UART2 clock (from CMU_TOP)
135 - description: USI0 clock (from CMU_TOP)
136 - description: USI1 clock (from CMU_TOP)
137 - description: USI2 clock (from CMU_TOP)
139 clock-names:
141 - const: oscclk
142 - const: dout_peri_bus
143 - const: dout_peri_spi0
144 - const: dout_peri_spi1
145 - const: dout_peri_uart0
146 - const: dout_peri_uart1
147 - const: dout_peri_uart2
148 - const: dout_peri_usi0
149 - const: dout_peri_usi1
150 - const: dout_peri_usi2
153 - compatible
154 - "#clock-cells"
155 - clocks
156 - clock-names
157 - reg
163 - |
164 #include <dt-bindings/clock/exynos7885.h>
166 cmu_peri: clock-controller@10010000 {
167 compatible = "samsung,exynos7885-cmu-peri";
169 #clock-cells = <1>;
181 clock-names = "oscclk",