Lines Matching +full:user +full:- +full:programmable
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The 5P35023 is a VersaClock programmable clock generator and
14 is designed for low-power, consumer, and high-performance PCI
16 architecture design, and each PLL is individually programmable
19 An internal OTP memory allows the user to store the configuration
20 in the device. After power up, the user can change the device register
29 …renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3…
34 - renesas,5p35023
39 '#clock-cells':
41 The index in the assigned-clocks is mapped to the output clock as below
42 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
52 $ref: /schemas/types.yaml#/definitions/uint8-array
56 - compatible
57 - reg
58 - '#clock-cells'
59 - clocks
64 - |
66 #address-cells = <1>;
67 #size-cells = <0>;
69 versa3: clock-generator@68 {
72 #clock-cells = <1>;
82 assigned-clocks = <&versa3 0>, <&versa3 1>,
85 assigned-clock-rates = <24000000>, <11289600>,