Lines Matching +full:power +full:- +full:on
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
27 clock-names:
29 - const: pclk
30 - const: clk32k_in
39 Must contain an entry for each entry in clock-names.
40 See ../clocks/clocks-bindings.txt for details.
42 '#clock-cells':
50 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
53 '#interrupt-cells':
59 interrupt-controller: true
61 nvidia,invert-interrupt:
64 The PMU is an external Power Management Unit, whose interrupt output
69 nvidia,core-power-req-active-high:
71 description: Core power request active-high.
73 nvidia,sys-clock-req-active-high:
75 description: System clock request active-high.
77 nvidia,combined-power-req:
79 description: combined power request for CPU and Core.
81 nvidia,cpu-pwr-good-en:
84 CPU power good signal from external PMIC to PMC is enabled.
86 nvidia,suspend-mode:
91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
92 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
95 nvidia,cpu-pwr-good-time:
97 description: CPU power good time in uSec.
99 nvidia,cpu-pwr-off-time:
101 description: CPU power off time in uSec.
103 nvidia,core-pwr-good-time:
104 $ref: /schemas/types.yaml#/definitions/uint32-array
106 <Oscillator-stable-time Power-stable-time>
107 Core power good time in uSec.
109 nvidia,core-pwr-off-time:
111 description: Core power off time in uSec.
113 nvidia,lp0-vec:
114 $ref: /schemas/types.yaml#/definitions/uint32-array
119 The AVP (Audio-Video Processor) is an ARM7 processor and
120 always being the first boot processor when chip is power on
126 core-supply:
128 Phandle to voltage regulator connected to the SoC Core power rail.
130 core-domain:
134 Core power domain, which has a dedicated voltage rail that powers
138 operating-points-v2:
140 Should contain level, voltages and opp-supported-hw property.
141 The supported-hw is a bitfield indicating SoC speedo or process
144 "#power-domain-cells":
148 - operating-points-v2
149 - "#power-domain-cells"
153 i2c-thermtrip:
156 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
157 hardware-triggered thermal reset will be enabled.
160 nvidia,i2c-controller-id:
168 nvidia,bus-addr:
170 description: Bus address of the PMU on the I2C bus.
172 nvidia,reg-addr:
176 nvidia,reg-data:
180 nvidia,pinmux-id:
188 - nvidia,i2c-controller-id
189 - nvidia,bus-addr
190 - nvidia,reg-addr
191 - nvidia,reg-data
198 This node contains a hierarchy of power domain nodes, which should
199 match the powergates on the Tegra SoC. Each powergate node
200 represents a power-domain on the Tegra SoC that can be power-gated
202 Hardware blocks belonging to a power domain should contain
203 "power-domains" property that is a phandle pointing to corresponding
208 Please refer to Tegra TRM for mode details on the powergate nodes to
209 use for each power-gate block inside Tegra.
235 "^[a-z0-9]+$":
245 for controlling a power-gate.
246 See ../clocks/clock-bindings.txt document for more details.
253 for controlling a power-gate.
256 power-domains:
259 '#power-domain-cells':
264 - clocks
265 - resets
266 - '#power-domain-cells'
271 "^[a-f0-9]+-[a-f0-9]+$":
274 This is a Pad configuration node. On Tegra SOCs a pad is a set of
276 attribute of the hardware. The PMC can be used to set pad power state
277 and signaling voltage. A pad can be either in active or power down mode.
278 The support for power state and signaling voltage configuration varies
279 depending on the pad in question. 3.3V and 1.8V signaling voltages
280 are supported on pins where software controllable signaling voltage
285 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
289 The following pads are present on Tegra124 and Tegra132
291 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
294 The following pads are present on Tegra210
295 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
296 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
297 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
298 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
305 low-power-enable:
307 description: Configure the pad into power down mode.
309 low-power-disable:
313 power-source:
319 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
320 Power state can be configured on all Tegra124 and Tegra132
323 All of the listed Tegra210 pads except pex-cntrl support power
325 on below Tegra210 pads.
326 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
327 sdmmc3, spi, spi-hv, and uart.
330 - pins
335 - compatible
336 - reg
337 - clock-names
338 - clocks
339 - '#clock-cells'
344 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
345 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
346 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
349 - |
351 #include <dt-bindings/clock/tegra210-car.h>
352 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
353 #include <dt-bindings/soc/tegra-pmc.h>
356 compatible = "nvidia,tegra210-pmc";
358 core-supply = <®ulator>;
360 clock-names = "pclk", "clk32k_in";
361 #clock-cells = <1>;
363 nvidia,invert-interrupt;
364 nvidia,suspend-mode = <0>;
365 nvidia,cpu-pwr-good-time = <0>;
366 nvidia,cpu-pwr-off-time = <0>;
367 nvidia,core-pwr-good-time = <4587 3876>;
368 nvidia,core-pwr-off-time = <39065>;
369 nvidia,core-power-req-active-high;
370 nvidia,sys-clock-req-active-high;
372 pd_core: core-domain {
373 operating-points-v2 = <&core_opp_table>;
374 #power-domain-cells = <0>;
382 power-domains = <&pd_core>;
383 #power-domain-cells = <0>;
389 power-domains = <&pd_core>;
390 #power-domain-cells = <0>;