Lines Matching +full:address +full:- +full:translation
1 .. SPDX-License-Identifier: GPL-2.0
17 PCIe Address Translation Services (ATS) along with Page Request Interface
19 application page-faults. For more information please refer to the PCIe
26 sync. When an ATS lookup fails for a virtual address, the device should
27 use the PRI in order to request the virtual address to be paged into the
29 translation before use.
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
39 executed in the hardware by SWQ interface, SIOV uses Process Address Space
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
52 performed, virtual addresses of all parameters, virtual address of a completion
53 record, and the PASID (process address space ID) of the current process.
55 ENQCMD works with non-posted semantics and carries a status back if the
64 Process Address Space Tagging
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
71 that sets up the routing for DMA and page-requests.
76 - Allocate the PASID, and program the process page-table (%cr3 register) in the
78 - Register for mmu_notifier() to track any page-table invalidations to keep
79 the device TLB in sync. For example, when a page-table entry is invalidated,
81 future access by the device to this virtual address to participate in
96 ENQCMD instruction, the PASID field in the descriptor is auto-filled with the
99 perform address translation. The IOMMU APIs setup the corresponding PASID
100 entry in IOMMU with the process address used by the CPU (e.g. %cr3 register in
110 PASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.
112 Only processes that access SVA-capable devices need to have a PASID
113 allocated. This allocation happens when a process opens/binds an SVA-capable
126 and returns so that the ENQCMD instruction is re-executed.
129 longer has the same address space that it had when the device was opened.
131 On clone(2) the new task shares the same address space, so will be
163 * The single process-wide PASID is used by all threads to interact
165 thread or each thread<->device pair.
173 work in the same address space, i.e., to share it. Some call it Shared
180 A Process Address Space ID (PASID) is a PCIe-defined Transaction Layer Packet
181 (TLP) prefix. A PASID is a 20-bit number allocated and managed by the OS.
189 Each doorbell is required to be spaced 4k (or page-size) apart for process
203 SWQ allows hardware to provision just a single address in the device. When
215 * Is this the same as SR-IOV?
217 Single Root I/O Virtualization (SR-IOV) focuses on providing independent
220 BARs, space for interrupts via MSI-X, its own register layout.
229 demand. SR-IOV creation and management is very static in nature. Consult
234 Creating PCIe SR-IOV type Virtual Functions (VF) is expensive. VFs require
235 duplicated hardware for PCI config space and interrupts such as MSI-X.
240 creates a software-defined device where all the configuration and control
247 with setting up a translation table to translate from Guest PASID to Host
258 Device TLB support - Device requests the IOMMU to lookup an address before
259 use via Address Translation Service (ATS) requests. If the mapping exists
263 Device requests the virtual address to be mapped via Page Request
266 a translation and continues.
268 IOMMU works with the OS in managing consistency of page-tables with the
276 VT-D:
277 https://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o…
280 https://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux
283 …intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-re…
286 https://software.intel.com/sites/default/files/341204-intel-data-streaming-accelerator-spec.pdf