Lines Matching +full:5 +full:a

27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
38 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
53   $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
54   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
60 specified as a bitmap::
62   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
72   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
76 3. Datasrc allows the user to check where the data comes from. It is 5 bits.
79 - 5'b00001: comes from L3C in this die;
80 - 5'b01000: comes from L3C in the cross-die;
81 - 5'b01001: comes from L3C which is in another socket;
82 - 5'b01110: comes from the local DDR;
83 - 5'b01111: comes from the cross-die DDR;
84 - 5'b10000: comes from cross-socket DDR;
90   $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
91   hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
96 SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
99 - 5'b00000: I/O_MGMT_ICL;
100 - 5'b00001: Network_ICL;
101 - 5'b00011: HAC_ICL;
102 - 5'b10000: PCIe_ICL;
104 5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
115 tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
123 Also attach to a task is unsupported as the events are all uncore.
125 Note: Please contact the maintainer for a complete list of events supported for