Lines Matching refs:msr
48 static void guest_msr(struct msr_data *msr) in guest_msr() argument
53 GUEST_ASSERT(msr->idx); in guest_msr()
55 if (!msr->write) in guest_msr()
56 vector = rdmsr_safe(msr->idx, &ignored); in guest_msr()
58 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
60 if (msr->available) in guest_msr()
61 GUEST_ASSERT_2(!vector, msr->idx, vector); in guest_msr()
63 GUEST_ASSERT_2(vector == GP_VECTOR, msr->idx, vector); in guest_msr()
118 struct msr_data *msr; in guest_test_msrs_access() local
125 msr = addr_gva2hva(vm, msr_gva); in guest_test_msrs_access()
155 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
156 msr->write = 0; in guest_test_msrs_access()
157 msr->available = 0; in guest_test_msrs_access()
160 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
161 msr->write = 0; in guest_test_msrs_access()
162 msr->available = 0; in guest_test_msrs_access()
170 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
171 msr->write = 1; in guest_test_msrs_access()
172 msr->write_val = LINUX_OS_ID; in guest_test_msrs_access()
173 msr->available = 1; in guest_test_msrs_access()
176 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
177 msr->write = 0; in guest_test_msrs_access()
178 msr->available = 1; in guest_test_msrs_access()
181 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
182 msr->write = 0; in guest_test_msrs_access()
183 msr->available = 1; in guest_test_msrs_access()
187 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
188 msr->write = 0; in guest_test_msrs_access()
189 msr->available = 0; in guest_test_msrs_access()
193 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
194 msr->write = 0; in guest_test_msrs_access()
195 msr->available = 1; in guest_test_msrs_access()
199 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
200 msr->write = 1; in guest_test_msrs_access()
201 msr->write_val = 1; in guest_test_msrs_access()
202 msr->available = 0; in guest_test_msrs_access()
206 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
207 msr->write = 0; in guest_test_msrs_access()
208 msr->available = 0; in guest_test_msrs_access()
212 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
213 msr->write = 0; in guest_test_msrs_access()
214 msr->available = 1; in guest_test_msrs_access()
218 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
219 msr->write = 1; in guest_test_msrs_access()
220 msr->write_val = 1; in guest_test_msrs_access()
221 msr->available = 0; in guest_test_msrs_access()
225 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
226 msr->write = 0; in guest_test_msrs_access()
227 msr->available = 0; in guest_test_msrs_access()
231 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
232 msr->write = 0; in guest_test_msrs_access()
233 msr->available = 1; in guest_test_msrs_access()
237 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
238 msr->write = 1; in guest_test_msrs_access()
239 msr->write_val = 1; in guest_test_msrs_access()
240 msr->available = 0; in guest_test_msrs_access()
244 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
245 msr->write = 0; in guest_test_msrs_access()
246 msr->available = 0; in guest_test_msrs_access()
250 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
251 msr->write = 0; in guest_test_msrs_access()
252 msr->available = 1; in guest_test_msrs_access()
255 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
256 msr->write = 1; in guest_test_msrs_access()
257 msr->write_val = 0; in guest_test_msrs_access()
258 msr->available = 1; in guest_test_msrs_access()
262 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
263 msr->write = 0; in guest_test_msrs_access()
264 msr->available = 0; in guest_test_msrs_access()
268 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
269 msr->write = 0; in guest_test_msrs_access()
270 msr->available = 1; in guest_test_msrs_access()
273 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
274 msr->write = 1; in guest_test_msrs_access()
275 msr->write_val = 0; in guest_test_msrs_access()
276 msr->available = 1; in guest_test_msrs_access()
280 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
281 msr->write = 0; in guest_test_msrs_access()
282 msr->available = 0; in guest_test_msrs_access()
289 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
290 msr->write = 0; in guest_test_msrs_access()
291 msr->available = 0; in guest_test_msrs_access()
295 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
296 msr->write = 0; in guest_test_msrs_access()
297 msr->available = 1; in guest_test_msrs_access()
300 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
301 msr->write = 1; in guest_test_msrs_access()
302 msr->write_val = 0; in guest_test_msrs_access()
303 msr->available = 1; in guest_test_msrs_access()
307 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
308 msr->write = 0; in guest_test_msrs_access()
309 msr->available = 0; in guest_test_msrs_access()
313 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
314 msr->write = 0; in guest_test_msrs_access()
315 msr->available = 1; in guest_test_msrs_access()
318 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
319 msr->write = 1; in guest_test_msrs_access()
320 msr->write_val = 0; in guest_test_msrs_access()
321 msr->available = 1; in guest_test_msrs_access()
325 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
326 msr->write = 1; in guest_test_msrs_access()
327 msr->write_val = 1 << 12; in guest_test_msrs_access()
328 msr->available = 0; in guest_test_msrs_access()
332 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
333 msr->write = 1; in guest_test_msrs_access()
334 msr->write_val = 1 << 12; in guest_test_msrs_access()
335 msr->available = 1; in guest_test_msrs_access()
339 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
340 msr->write = 0; in guest_test_msrs_access()
341 msr->available = 0; in guest_test_msrs_access()
345 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
346 msr->write = 1; in guest_test_msrs_access()
347 msr->write_val = 1; in guest_test_msrs_access()
348 msr->available = 1; in guest_test_msrs_access()
352 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
353 msr->write = 0; in guest_test_msrs_access()
354 msr->available = 0; in guest_test_msrs_access()
358 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
359 msr->write = 0; in guest_test_msrs_access()
360 msr->available = 1; in guest_test_msrs_access()
364 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
365 msr->write = 1; in guest_test_msrs_access()
366 msr->write_val = 1; in guest_test_msrs_access()
367 msr->available = 0; in guest_test_msrs_access()
371 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
372 msr->write = 0; in guest_test_msrs_access()
373 msr->available = 0; in guest_test_msrs_access()
377 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
378 msr->write = 0; in guest_test_msrs_access()
379 msr->available = 1; in guest_test_msrs_access()
382 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
383 msr->write = 1; in guest_test_msrs_access()
384 msr->write_val = 1; in guest_test_msrs_access()
385 msr->available = 1; in guest_test_msrs_access()
389 msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; in guest_test_msrs_access()
390 msr->write = 1; in guest_test_msrs_access()
391 msr->write_val = 1; in guest_test_msrs_access()
392 msr->available = 0; in guest_test_msrs_access()
396 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
397 msr->write = 0; in guest_test_msrs_access()
398 msr->available = 0; in guest_test_msrs_access()
402 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
403 msr->write = 0; in guest_test_msrs_access()
404 msr->available = 1; in guest_test_msrs_access()
407 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
408 msr->write = 1; in guest_test_msrs_access()
409 msr->write_val = 1; in guest_test_msrs_access()
410 msr->available = 1; in guest_test_msrs_access()
414 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
415 msr->write = 0; in guest_test_msrs_access()
416 msr->available = 0; in guest_test_msrs_access()
421 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
422 msr->write = 0; in guest_test_msrs_access()
423 msr->available = 1; in guest_test_msrs_access()
426 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
427 msr->write = 1; in guest_test_msrs_access()
428 msr->write_val = 0; in guest_test_msrs_access()
429 msr->available = 1; in guest_test_msrs_access()
442 msr->idx, msr->write ? "write" : "read"); in guest_test_msrs_access()