Lines Matching +full:0 +full:x21
37 cmp x2, #0
39 0: ldrb w3, [x1], #1
42 b.ne 0b
56 // bits 7: 0 32-bit lane index
67 0: str w3, [x0], #4
70 b.ne 0b
108 stp x0, x1, [sp, #-0x20]!
109 str x2, [sp, #0x10]
111 mov x5, #0
112 0: ldrb w3, [x0, x5]
118 b.ne 0b
120 1: ldr x2, [sp, #0x10]
121 ldp x0, x1, [sp], #0x20
160 #if 0
193 mov x0, #0
195 svc #0
217 mov x2, #0
220 svc #0
235 mov x23, #0 // signal count
284 svc #0
291 mov x22, #0 // generation number, increments per iteration
293 rdsvl 0, 8
298 0: mov x0, x20
299 sub x1, x21, #1
302 subs x21, x21, #1
303 b.ne 0b
307 svc #0
309 mrs x0, S3_3_C4_C2_2 // SVCR should have ZA=1,SM=0
316 0: sub x0, x24, x21
318 subs x21, x21, #1
319 bne 0b
325 mov x0, #0
328 svc #0
333 // ldr w0, =0xdeadc0de
335 // svc #0
349 mov x0, x21
362 svc #0
364 // ldr w0, =0xdeadc0de
366 // svc #0
370 svc #0
373 // svc #0
385 svc #0
397 svc #0