Lines Matching +full:0 +full:- +full:7
5 "Counter": "0,1,2,3,4,5,6,7",
7 "EventCode": "0x14",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
12 "UMask": "0x9"
17 "Counter": "0,1,2,3,4,5,6,7",
18 "EventCode": "0xc1",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
23 "UMask": "0x7"
28 "Counter": "0,1,2,3,4,5,6,7",
29 "EventCode": "0xc4",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
39 "Counter": "0,1,2,3,4,5,6,7",
40 "EventCode": "0xc4",
43 "PEBScounters": "0,1,2,3,4,5,6,7",
46 "UMask": "0x11"
51 "Counter": "0,1,2,3,4,5,6,7",
52 "EventCode": "0xc4",
55 "PEBScounters": "0,1,2,3,4,5,6,7",
58 "UMask": "0x10"
63 "Counter": "0,1,2,3,4,5,6,7",
64 "EventCode": "0xc4",
67 "PEBScounters": "0,1,2,3,4,5,6,7",
70 "UMask": "0x1"
75 "Counter": "0,1,2,3,4,5,6,7",
76 "EventCode": "0xc4",
79 "PEBScounters": "0,1,2,3,4,5,6,7",
82 "UMask": "0x40"
87 "Counter": "0,1,2,3,4,5,6,7",
88 "EventCode": "0xc4",
91 "PEBScounters": "0,1,2,3,4,5,6,7",
94 "UMask": "0x80"
99 "Counter": "0,1,2,3,4,5,6,7",
100 "EventCode": "0xc4",
103 "PEBScounters": "0,1,2,3,4,5,6,7",
106 "UMask": "0x2"
111 "Counter": "0,1,2,3,4,5,6,7",
112 "EventCode": "0xc4",
115 "PEBScounters": "0,1,2,3,4,5,6,7",
118 "UMask": "0x8"
123 "Counter": "0,1,2,3,4,5,6,7",
124 "EventCode": "0xc4",
127 "PEBScounters": "0,1,2,3,4,5,6,7",
130 "UMask": "0x20"
135 "Counter": "0,1,2,3,4,5,6,7",
136 "EventCode": "0xc5",
139 "PEBScounters": "0,1,2,3,4,5,6,7",
146 "Counter": "0,1,2,3,4,5,6,7",
147 "EventCode": "0xc5",
150 "PEBScounters": "0,1,2,3,4,5,6,7",
153 "UMask": "0x11"
156 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
158 "Counter": "0,1,2,3,4,5,6,7",
159 "EventCode": "0xc5",
162 "PEBScounters": "0,1,2,3,4,5,6,7",
165 "UMask": "0x10"
170 "Counter": "0,1,2,3,4,5,6,7",
171 "EventCode": "0xc5",
174 "PEBScounters": "0,1,2,3,4,5,6,7",
177 "UMask": "0x1"
180 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
182 "Counter": "0,1,2,3,4,5,6,7",
183 "EventCode": "0xc5",
186 "PEBScounters": "0,1,2,3,4,5,6,7",
187 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
189 "UMask": "0x80"
194 "Counter": "0,1,2,3,4,5,6,7",
195 "EventCode": "0xc5",
198 "PEBScounters": "0,1,2,3,4,5,6,7",
201 "UMask": "0x2"
206 "Counter": "0,1,2,3,4,5,6,7",
207 "EventCode": "0xc5",
210 "PEBScounters": "0,1,2,3,4,5,6,7",
213 "UMask": "0x20"
218 "Counter": "0,1,2,3,4,5,6,7",
219 "EventCode": "0xec",
221 "PEBScounters": "0,1,2,3,4,5,6,7",
224 "UMask": "0x2"
229 "Counter": "0,1,2,3,4,5,6,7",
230 "EventCode": "0x3c",
232 "PEBScounters": "0,1,2,3,4,5,6,7",
235 "UMask": "0x2"
240 "Counter": "0,1,2,3,4,5,6,7",
241 "EventCode": "0x3c",
243 "PEBScounters": "0,1,2,3,4,5,6,7",
244 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
246 "UMask": "0x8"
256 "UMask": "0x3"
261 "Counter": "0,1,2,3,4,5,6,7",
262 "EventCode": "0x3c",
264 "PEBScounters": "0,1,2,3,4,5,6,7",
267 "UMask": "0x1"
277 "UMask": "0x2"
282 "Counter": "0,1,2,3,4,5,6,7",
283 "EventCode": "0x3c",
285 "PEBScounters": "0,1,2,3,4,5,6,7",
292 "Counter": "0,1,2,3",
294 "EventCode": "0xa3",
296 "PEBScounters": "0,1,2,3",
298 "UMask": "0x8"
303 "Counter": "0,1,2,3",
305 "EventCode": "0xa3",
307 "PEBScounters": "0,1,2,3",
309 "UMask": "0x1"
314 "Counter": "0,1,2,3,4,5,6,7",
316 "EventCode": "0xa3",
318 "PEBScounters": "0,1,2,3,4,5,6,7",
320 "UMask": "0x10"
325 "Counter": "0,1,2,3",
327 "EventCode": "0xa3",
329 "PEBScounters": "0,1,2,3",
331 "UMask": "0xc"
336 "Counter": "0,1,2,3",
338 "EventCode": "0xa3",
340 "PEBScounters": "0,1,2,3",
342 "UMask": "0x5"
347 "Counter": "0,1,2,3,4,5,6,7",
349 "EventCode": "0xa3",
351 "PEBScounters": "0,1,2,3,4,5,6,7",
353 "UMask": "0x14"
358 "Counter": "0,1,2,3,4,5,6,7",
360 "EventCode": "0xa3",
362 "PEBScounters": "0,1,2,3,4,5,6,7",
364 "UMask": "0x4"
369 "Counter": "0,1,2,3,4,5,6,7",
370 "EventCode": "0xa6",
372 "PEBScounters": "0,1,2,3,4,5,6,7",
375 "UMask": "0x2"
380 "Counter": "0,1,2,3,4,5,6,7",
381 "EventCode": "0xa6",
383 "PEBScounters": "0,1,2,3,4,5,6,7",
386 "UMask": "0x4"
391 "Counter": "0,1,2,3,4,5,6,7",
392 "EventCode": "0xa6",
394 "PEBScounters": "0,1,2,3,4,5,6,7",
397 "UMask": "0x8"
402 "Counter": "0,1,2,3,4,5,6,7",
403 "EventCode": "0xa6",
405 "PEBScounters": "0,1,2,3,4,5,6,7",
408 "UMask": "0x10"
413 "Counter": "0,1,2,3,4,5,6,7",
415 "EventCode": "0xa6",
417 "PEBScounters": "0,1,2,3,4,5,6,7",
420 "UMask": "0x21"
425 "Counter": "0,1,2,3,4,5,6,7",
427 "EventCode": "0xa6",
429 "PEBScounters": "0,1,2,3,4,5,6,7",
432 "UMask": "0x40"
437 "Counter": "0,1,2,3,4,5,6,7",
438 "EventCode": "0xa6",
440 "PEBScounters": "0,1,2,3,4,5,6,7",
441 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
443 "UMask": "0x80"
448 "Counter": "0,1,2,3",
449 "EventCode": "0x87",
451 "PEBScounters": "0,1,2,3",
452 …0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the num…
454 "UMask": "0x1"
459 "Counter": "0,1,2,3",
460 "EventCode": "0x55",
462 "PEBScounters": "0,1,2,3",
465 "UMask": "0x1"
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
470 "Counter": "Fixed counter 0",
474 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
476 "UMask": "0x1"
479 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
481 "Counter": "0,1,2,3,4,5,6,7",
482 "EventCode": "0xc0",
485 "PEBScounters": "0,1,2,3,4,5,6,7",
486 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
492 "Counter": "0,1,2,3,4,5,6,7",
493 "EventCode": "0xc0",
496 "PEBScounters": "0,1,2,3,4,5,6,7",
498 "UMask": "0x2"
503 "Counter": "Fixed counter 0",
507 …R) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
509 "UMask": "0x1"
512 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
514 "Counter": "0,1,2,3,4,5,6,7",
516 "EventCode": "0x0d",
518 "PEBScounters": "0,1,2,3,4,5,6,7",
519 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
521 "UMask": "0x3"
526 "Counter": "0,1,2,3,4,5,6,7",
527 "EventCode": "0x0d",
529 "PEBScounters": "0,1,2,3,4,5,6,7",
532 "UMask": "0x80"
537 "Counter": "0,1,2,3,4,5,6,7",
538 "EventCode": "0x0d",
540 "PEBScounters": "0,1,2,3,4,5,6,7",
543 "UMask": "0x1"
548 "Counter": "0,1,2,3,4,5,6,7",
549 "EventCode": "0x0d",
551 "PEBScounters": "0,1,2,3,4,5,6,7",
552 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
554 "UMask": "0x10"
559 "Counter": "0,1,2,3",
560 "EventCode": "0x03",
562 "PEBScounters": "0,1,2,3",
565 "UMask": "0x8"
570 "Counter": "0,1,2,3",
571 "EventCode": "0x03",
573 "PEBScounters": "0,1,2,3",
576 "UMask": "0x2"
581 "Counter": "0,1,2,3",
582 "EventCode": "0x07",
584 "PEBScounters": "0,1,2,3",
587 "UMask": "0x1"
592 "Counter": "0,1,2,3",
593 "EventCode": "0x4c",
595 "PEBScounters": "0,1,2,3",
596 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
598 "UMask": "0x1"
603 "Counter": "0,1,2,3",
605 "EventCode": "0xa8",
607 "PEBScounters": "0,1,2,3",
608 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
610 "UMask": "0x1"
615 "Counter": "0,1,2,3",
617 "EventCode": "0xa8",
619 "PEBScounters": "0,1,2,3",
620 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
622 "UMask": "0x1"
627 "Counter": "0,1,2,3",
628 "EventCode": "0xa8",
630 "PEBScounters": "0,1,2,3",
631 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
633 "UMask": "0x1"
638 "Counter": "0,1,2,3,4,5,6,7",
641 "EventCode": "0xc3",
643 "PEBScounters": "0,1,2,3,4,5,6,7",
646 "UMask": "0x1"
649 "BriefDescription": "Self-modifying code (SMC) detected.",
651 "Counter": "0,1,2,3,4,5,6,7",
652 "EventCode": "0xc3",
654 "PEBScounters": "0,1,2,3,4,5,6,7",
655 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
657 "UMask": "0x4"
662 "Counter": "0,1,2,3,4,5,6,7",
663 "EventCode": "0xcc",
665 "PEBScounters": "0,1,2,3,4,5,6,7",
668 "UMask": "0x20"
672 "Counter": "0,1,2,3,4,5,6,7",
673 "EventCode": "0xcc",
677 "UMask": "0x40"
682 "Counter": "0,1,2,3,4,5,6,7",
683 "EventCode": "0xa2",
685 "PEBScounters": "0,1,2,3,4,5,6,7",
686 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
688 "UMask": "0x8"
693 "Counter": "0,1,2,3,4,5,6,7",
694 "EventCode": "0xa2",
696 "PEBScounters": "0,1,2,3,4,5,6,7",
698 "UMask": "0x2"
703 "Counter": "0,1,2,3,4,5,6,7",
704 "EventCode": "0x5e",
706 "PEBScounters": "0,1,2,3,4,5,6,7",
707 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
709 "UMask": "0x1"
714 "Counter": "0,1,2,3,4,5,6,7",
717 "EventCode": "0x5e",
720 "PEBScounters": "0,1,2,3,4,5,6,7",
721 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
723 "UMask": "0x1"
726 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
728 "Counter": "0,1,2,3,4,5,6,7",
729 "EventCode": "0xa4",
731 "PEBScounters": "0,1,2,3,4,5,6,7",
732 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
734 "UMask": "0x2"
739 "Counter": "0,1,2,3,4,5,6,7",
740 "EventCode": "0xa4",
742 "PEBScounters": "0,1,2,3,4,5,6,7",
743 …t were issued but not retired from the specualtive path as well as the out-of-order engine recover…
745 "UMask": "0x8"
748 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
753 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
755 "UMask": "0x4"
758 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
760 "Counter": "0,1,2,3,4,5,6,7",
761 "EventCode": "0xa4",
763 "PEBScounters": "0,1,2,3,4,5,6,7",
764 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
766 "UMask": "0x1"
769 … "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
771 "Counter": "0,1,2,3",
772 "EventCode": "0x56",
774 "PEBScounters": "0,1,2,3",
775 "PublicDescription": "Uops exclusively fetched by decoder 0",
777 "UMask": "0x1"
780 "BriefDescription": "Number of uops executed on port 0",
782 "Counter": "0,1,2,3,4,5,6,7",
783 "EventCode": "0xa1",
785 "PEBScounters": "0,1,2,3,4,5,6,7",
786 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
788 "UMask": "0x1"
793 "Counter": "0,1,2,3,4,5,6,7",
794 "EventCode": "0xa1",
796 "PEBScounters": "0,1,2,3,4,5,6,7",
797 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
799 "UMask": "0x2"
804 "Counter": "0,1,2,3,4,5,6,7",
805 "EventCode": "0xa1",
807 "PEBScounters": "0,1,2,3,4,5,6,7",
808 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
810 "UMask": "0x4"
815 "Counter": "0,1,2,3,4,5,6,7",
816 "EventCode": "0xa1",
818 "PEBScounters": "0,1,2,3,4,5,6,7",
819 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
821 "UMask": "0x10"
826 "Counter": "0,1,2,3,4,5,6,7",
827 "EventCode": "0xa1",
829 "PEBScounters": "0,1,2,3,4,5,6,7",
830 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
832 "UMask": "0x20"
837 "Counter": "0,1,2,3,4,5,6,7",
838 "EventCode": "0xa1",
840 "PEBScounters": "0,1,2,3,4,5,6,7",
841 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
843 "UMask": "0x40"
846 "BriefDescription": "Number of uops executed on port 7 and 8",
848 "Counter": "0,1,2,3,4,5,6,7",
849 "EventCode": "0xa1",
851 "PEBScounters": "0,1,2,3,4,5,6,7",
852 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
854 "UMask": "0x80"
859 "Counter": "0,1,2,3,4,5,6,7",
860 "EventCode": "0xb1",
862 "PEBScounters": "0,1,2,3,4,5,6,7",
865 "UMask": "0x2"
868 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
870 "Counter": "0,1,2,3,4,5,6,7",
872 "EventCode": "0xb1",
874 "PEBScounters": "0,1,2,3,4,5,6,7",
875 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
877 "UMask": "0x2"
880 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
882 "Counter": "0,1,2,3,4,5,6,7",
884 "EventCode": "0xb1",
886 "PEBScounters": "0,1,2,3,4,5,6,7",
887 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
889 "UMask": "0x2"
892 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
894 "Counter": "0,1,2,3,4,5,6,7",
896 "EventCode": "0xb1",
898 "PEBScounters": "0,1,2,3,4,5,6,7",
899 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
901 "UMask": "0x2"
904 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
906 "Counter": "0,1,2,3,4,5,6,7",
908 "EventCode": "0xb1",
910 "PEBScounters": "0,1,2,3,4,5,6,7",
911 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
913 "UMask": "0x2"
916 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
918 "Counter": "0,1,2,3,4,5,6,7",
920 "EventCode": "0xb1",
922 "PEBScounters": "0,1,2,3,4,5,6,7",
923 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
925 "UMask": "0x1"
928 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
930 "Counter": "0,1,2,3,4,5,6,7",
932 "EventCode": "0xb1",
934 "PEBScounters": "0,1,2,3,4,5,6,7",
935 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
937 "UMask": "0x1"
940 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
942 "Counter": "0,1,2,3,4,5,6,7",
944 "EventCode": "0xb1",
946 "PEBScounters": "0,1,2,3,4,5,6,7",
947 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
949 "UMask": "0x1"
952 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
954 "Counter": "0,1,2,3,4,5,6,7",
956 "EventCode": "0xb1",
958 "PEBScounters": "0,1,2,3,4,5,6,7",
959 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
961 "UMask": "0x1"
966 "Counter": "0,1,2,3,4,5,6,7",
968 "EventCode": "0xb1",
971 "PEBScounters": "0,1,2,3,4,5,6,7",
974 "UMask": "0x1"
977 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
979 "Counter": "0,1,2,3,4,5,6,7",
980 "EventCode": "0xb1",
982 "PEBScounters": "0,1,2,3,4,5,6,7",
984 "UMask": "0x1"
989 "Counter": "0,1,2,3,4,5,6,7",
990 "EventCode": "0xb1",
992 "PEBScounters": "0,1,2,3,4,5,6,7",
995 "UMask": "0x10"
1000 "Counter": "0,1,2,3,4,5,6,7",
1001 "EventCode": "0x0e",
1003 "PEBScounters": "0,1,2,3,4,5,6,7",
1006 "UMask": "0x1"
1011 "Counter": "0,1,2,3,4,5,6,7",
1013 "EventCode": "0x0e",
1016 "PEBScounters": "0,1,2,3,4,5,6,7",
1019 "UMask": "0x1"
1022 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1024 "Counter": "0,1,2,3,4,5,6,7",
1025 "EventCode": "0x0e",
1027 "PEBScounters": "0,1,2,3,4,5,6,7",
1028 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1030 "UMask": "0x2"
1035 "Counter": "0,1,2,3,4,5,6,7",
1036 "EventCode": "0xc2",
1038 "PEBScounters": "0,1,2,3,4,5,6,7",
1041 "UMask": "0x2"
1046 "Counter": "0,1,2,3,4,5,6,7",
1048 "EventCode": "0xc2",
1051 "PEBScounters": "0,1,2,3,4,5,6,7",
1054 "UMask": "0x2"
1059 "Counter": "0,1,2,3,4,5,6,7",
1061 "EventCode": "0xc2",
1064 "PEBScounters": "0,1,2,3,4,5,6,7",
1067 "UMask": "0x2"