Lines Matching +full:front +full:- +full:end

3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
9 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
27         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
47 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
62 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
113         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
122 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
128 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
137 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
143 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
152 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
158         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
167 …ter an interval where the front-end delivered no uops for a period of at least 2 cycles which was …
173 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
182 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
188 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
197 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
203 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
212 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
218 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
227 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
233 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
242 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
248 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
257 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
263 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
272 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
304 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
310 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
315 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
321 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
449 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
461 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
466 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
474 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…