Lines Matching +full:3 +full:- +full:7
3 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3",
36 "Counter": "0,1,2,3",
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
48 "Counter": "0,1,2,3",
49 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3",
72 "CounterHTOff": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3",
84 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "Counter": "0,1,2,3",
108 "CounterHTOff": "0,1,2,3,4,5,6,7",
118 "Counter": "0,1,2,3",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
127 "Counter": "0,1,2,3",
128 "CounterHTOff": "0,1,2,3",
138 "Counter": "0,1,2,3",
139 "CounterHTOff": "0,1,2,3,4,5,6,7",
149 "Counter": "0,1,2,3",
150 "CounterHTOff": "0,1,2,3,4,5,6,7",
160 "Counter": "0,1,2,3",
161 "CounterHTOff": "0,1,2,3,4,5,6,7",
170 "Counter": "0,1,2,3",
171 "CounterHTOff": "0,1,2,3,4,5,6,7",
175 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
181 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7",
190 "Counter": "0,1,2,3",
191 "CounterHTOff": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3",
201 "CounterHTOff": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3",
210 "CounterHTOff": "0,1,2,3,4,5,6,7",
227 "Counter": "0,1,2,3",
228 "CounterHTOff": "0,1,2,3,4,5,6,7",
237 "Counter": "0,1,2,3",
238 "CounterHTOff": "0,1,2,3,4,5,6,7",
245 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
246 "Counter": "0,1,2,3",
247 "CounterHTOff": "0,1,2,3,4,5,6,7",
252 …Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
275 "Counter": "0,1,2,3",
276 "CounterHTOff": "0,1,2,3,4,5,6,7",
285 "Counter": "0,1,2,3",
286 "CounterHTOff": "0,1,2,3,4,5,6,7",
293 "Counter": "0,1,2,3",
294 "CounterHTOff": "0,1,2,3,4,5,6,7",
303 "Counter": "0,1,2,3",
304 "CounterHTOff": "0,1,2,3,4,5,6,7",
313 "Counter": "0,1,2,3",
314 "CounterHTOff": "0,1,2,3,4,5,6,7",
323 "Counter": "0,1,2,3",
324 "CounterHTOff": "0,1,2,3,4,5,6,7",
333 "Counter": "0,1,2,3",
334 "CounterHTOff": "0,1,2,3,4,5,6,7",
343 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3",
353 "Counter": "0,1,2,3",
354 "CounterHTOff": "0,1,2,3,4,5,6,7",
363 "Counter": "0,1,2,3",
364 "CounterHTOff": "0,1,2,3,4,5,6,7",
373 "Counter": "0,1,2,3",
374 "CounterHTOff": "0,1,2,3,4,5,6,7",
382 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
383 "Counter": "0,1,2,3",
384 "CounterHTOff": "0,1,2,3,4,5,6,7",
386 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
387 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
393 "Counter": "0,1,2,3",
394 "CounterHTOff": "0,1,2,3,4,5,6,7",
403 "Counter": "0,1,2,3",
404 "CounterHTOff": "0,1,2,3,4,5,6,7",
412 "Counter": "0,1,2,3",
413 "CounterHTOff": "0,1,2,3,4,5,6,7",
422 "Counter": "0,1,2,3",
423 "CounterHTOff": "0,1,2,3,4,5,6,7",
426 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
432 "Counter": "0,1,2,3",
433 "CounterHTOff": "0,1,2,3,4,5,6,7",
445 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro…
450 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
451 "Counter": "0,1,2,3",
452 "CounterHTOff": "0,1,2,3,4,5,6,7",
456 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
461 "Counter": "0,1,2,3",
462 "CounterHTOff": "0,1,2,3,4,5,6,7",
484 "Counter": "0,2,3",
485 "CounterHTOff": "0,2,3",
497 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path …
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3,4,5,6,7",
507 "Counter": "0,1,2,3",
508 "CounterHTOff": "0,1,2,3,4,5,6,7",
518 "Counter": "0,1,2,3",
519 "CounterHTOff": "0,1,2,3,4,5,6,7",
527 "Counter": "0,1,2,3",
528 "CounterHTOff": "0,1,2,3,4,5,6,7",
537 "Counter": "0,1,2,3",
538 "CounterHTOff": "0,1,2,3,4,5,6,7",
547 "Counter": "0,1,2,3",
548 "CounterHTOff": "0,1,2,3,4,5,6,7",
557 "Counter": "0,1,2,3",
558 "CounterHTOff": "0,1,2,3,4,5,6,7",
561 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
567 "Counter": "0,1,2,3",
568 "CounterHTOff": "0,1,2,3,4,5,6,7",
572 …"PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector…
578 "Counter": "0,1,2,3",
579 "CounterHTOff": "0,1,2,3,4,5,6,7",
583 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
589 "Counter": "0,1,2,3",
590 "CounterHTOff": "0,1,2,3,4,5,6,7",
593 … "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
599 "Counter": "0,1,2,3",
600 "CounterHTOff": "0,1,2,3,4,5,6,7",
609 "BriefDescription": "Self-modifying code (SMC) detected.",
610 "Counter": "0,1,2,3",
611 "CounterHTOff": "0,1,2,3,4,5,6,7",
614 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
619 …"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Exa…
620 "Counter": "0,1,2,3",
621 "CounterHTOff": "0,1,2,3,4,5,6,7",
629 "Counter": "0,1,2,3",
630 "CounterHTOff": "0,1,2,3,4,5,6,7",
638 "BriefDescription": "Resource-related stall cycles",
639 "Counter": "0,1,2,3",
640 "CounterHTOff": "0,1,2,3,4,5,6,7",
643 "PublicDescription": "Counts resource-related stall cycles.",
649 "Counter": "0,1,2,3",
650 "CounterHTOff": "0,1,2,3,4,5,6,7",
653 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
659 "Counter": "0,1,2,3",
660 "CounterHTOff": "0,1,2,3,4,5,6,7",
669 "Counter": "0,1,2,3",
670 "CounterHTOff": "0,1,2,3,4,5,6,7",
678 "Counter": "0,1,2,3",
679 "CounterHTOff": "0,1,2,3,4,5,6,7",
682 …ing which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thre…
688 "Counter": "0,1,2,3",
689 "CounterHTOff": "0,1,2,3,4,5,6,7",
695 …eservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound iss…
701 "Counter": "0,1,2,3",
702 "CounterHTOff": "0,1,2,3,4,5,6,7",
705 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
711 "Counter": "0,1,2,3",
712 "CounterHTOff": "0,1,2,3,4,5,6,7",
715 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
721 "Counter": "0,1,2,3",
722 "CounterHTOff": "0,1,2,3,4,5,6,7",
725 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
730 "BriefDescription": "Cycles per thread when uops are executed in port 3",
731 "Counter": "0,1,2,3",
732 "CounterHTOff": "0,1,2,3,4,5,6,7",
735 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
741 "Counter": "0,1,2,3",
742 "CounterHTOff": "0,1,2,3,4,5,6,7",
745 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
751 "Counter": "0,1,2,3",
752 "CounterHTOff": "0,1,2,3,4,5,6,7",
755 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
761 "Counter": "0,1,2,3",
762 "CounterHTOff": "0,1,2,3,4,5,6,7",
765 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
770 "BriefDescription": "Cycles per thread when uops are executed in port 7",
771 "Counter": "0,1,2,3",
772 "CounterHTOff": "0,1,2,3,4,5,6,7",
775 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
781 "Counter": "0,1,2,3",
782 "CounterHTOff": "0,1,2,3,4,5,6,7",
790 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
791 "Counter": "0,1,2,3",
792 "CounterHTOff": "0,1,2,3,4,5,6,7",
800 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
801 "Counter": "0,1,2,3",
802 "CounterHTOff": "0,1,2,3,4,5,6,7",
810 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
811 "Counter": "0,1,2,3",
812 "CounterHTOff": "0,1,2,3,4,5,6,7",
813 "CounterMask": "3",
820 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
821 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7",
830 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
831 "Counter": "0,1,2,3",
832 "CounterHTOff": "0,1,2,3,4,5,6,7",
841 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3,4,5,6,7",
847 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
852 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
858 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
863 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
864 "Counter": "0,1,2,3",
865 "CounterHTOff": "0,1,2,3,4,5,6,7",
866 "CounterMask": "3",
869 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
874 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
875 "Counter": "0,1,2,3",
876 "CounterHTOff": "0,1,2,3,4,5,6,7",
880 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
886 "Counter": "0,1,2,3",
887 "CounterHTOff": "0,1,2,3,4,5,6,7",
897 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7",
902 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
908 "Counter": "0,1,2,3",
909 "CounterHTOff": "0,1,2,3,4,5,6,7",
918 "Counter": "0,1,2,3",
919 "CounterHTOff": "0,1,2,3,4,5,6,7",
927 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
928 "Counter": "0,1,2,3",
929 "CounterHTOff": "0,1,2,3,4,5,6,7",
937 "Counter": "0,1,2,3",
938 "CounterHTOff": "0,1,2,3,4,5,6,7",
948 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
949 "Counter": "0,1,2,3",
950 "CounterHTOff": "0,1,2,3,4,5,6,7",
953 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
958 "BriefDescription": "Number of macro-fused uops retired. (non precise)",
959 "Counter": "0,1,2,3",
960 "CounterHTOff": "0,1,2,3,4,5,6,7",
963 "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
969 "Counter": "0,1,2,3",
970 "CounterHTOff": "0,1,2,3,4,5,6,7",
979 "Counter": "0,1,2,3",
980 "CounterHTOff": "0,1,2,3,4,5,6,7",
991 "Counter": "0,1,2,3",
992 "CounterHTOff": "0,1,2,3,4,5,6,7",