Lines Matching +full:0 +full:- +full:3
3 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
7 "EventCode": "0x14",
10 "UMask": "0x1"
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 "EventCode": "0xC4",
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3",
27 "EventCode": "0xC4",
32 "UMask": "0x4"
36 "Counter": "0,1,2,3",
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 "EventCode": "0xC4",
44 "UMask": "0x1"
48 "Counter": "0,1,2,3",
49 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "EventCode": "0xc4",
55 "UMask": "0x10"
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
62 "EventCode": "0xC4",
67 "UMask": "0x40"
71 "Counter": "0,1,2,3",
72 "CounterHTOff": "0,1,2,3,4,5,6,7",
74 "EventCode": "0xC4",
79 "UMask": "0x2"
83 "Counter": "0,1,2,3",
84 "CounterHTOff": "0,1,2,3,4,5,6,7",
86 "EventCode": "0xC4",
91 "UMask": "0x8"
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
98 "EventCode": "0xC4",
103 "UMask": "0x20"
107 "Counter": "0,1,2,3",
108 "CounterHTOff": "0,1,2,3,4,5,6,7",
110 "EventCode": "0xC4",
114 "UMask": "0x10"
118 "Counter": "0,1,2,3",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
120 "EventCode": "0xC5",
127 "Counter": "0,1,2,3",
128 "CounterHTOff": "0,1,2,3",
129 "EventCode": "0xC5",
134 "UMask": "0x4"
138 "Counter": "0,1,2,3",
139 "CounterHTOff": "0,1,2,3,4,5,6,7",
140 "EventCode": "0xC5",
145 "UMask": "0x1"
149 "Counter": "0,1,2,3",
150 "CounterHTOff": "0,1,2,3,4,5,6,7",
151 "EventCode": "0xC5",
156 "UMask": "0x2"
160 "Counter": "0,1,2,3",
161 "CounterHTOff": "0,1,2,3,4,5,6,7",
162 "EventCode": "0xC5",
166 "UMask": "0x20"
170 "Counter": "0,1,2,3",
171 "CounterHTOff": "0,1,2,3,4,5,6,7",
172 "EventCode": "0xC5",
175 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
177 "UMask": "0x8"
181 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7",
183 "EventCode": "0x3C",
186 "UMask": "0x2"
190 "Counter": "0,1,2,3",
191 "CounterHTOff": "0,1,2,3,4,5,6,7",
192 "EventCode": "0x3C",
195 "UMask": "0x1"
200 "Counter": "0,1,2,3",
201 "CounterHTOff": "0,1,2,3,4,5,6,7",
202 "EventCode": "0x3C",
205 "UMask": "0x1"
209 "Counter": "0,1,2,3",
210 "CounterHTOff": "0,1,2,3,4,5,6,7",
211 "EventCode": "0x3C",
214 "UMask": "0x2"
223 "UMask": "0x3"
227 "Counter": "0,1,2,3",
228 "CounterHTOff": "0,1,2,3,4,5,6,7",
229 "EventCode": "0x3C",
232 "UMask": "0x1"
237 "Counter": "0,1,2,3",
238 "CounterHTOff": "0,1,2,3,4,5,6,7",
239 "EventCode": "0x3C",
242 "UMask": "0x1"
245 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
246 "Counter": "0,1,2,3",
247 "CounterHTOff": "0,1,2,3,4,5,6,7",
250 "EventCode": "0x3C",
252 …Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
262 "UMask": "0x2"
271 "UMask": "0x2"
275 "Counter": "0,1,2,3",
276 "CounterHTOff": "0,1,2,3,4,5,6,7",
277 "EventCode": "0x3C",
285 "Counter": "0,1,2,3",
286 "CounterHTOff": "0,1,2,3,4,5,6,7",
287 "EventCode": "0x3C",
293 "Counter": "0,1,2,3",
294 "CounterHTOff": "0,1,2,3,4,5,6,7",
296 "EventCode": "0xA3",
299 "UMask": "0x8"
303 "Counter": "0,1,2,3",
304 "CounterHTOff": "0,1,2,3,4,5,6,7",
306 "EventCode": "0xA3",
309 "UMask": "0x1"
313 "Counter": "0,1,2,3",
314 "CounterHTOff": "0,1,2,3,4,5,6,7",
316 "EventCode": "0xA3",
319 "UMask": "0x10"
323 "Counter": "0,1,2,3",
324 "CounterHTOff": "0,1,2,3,4,5,6,7",
326 "EventCode": "0xA3",
329 "UMask": "0xc"
333 "Counter": "0,1,2,3",
334 "CounterHTOff": "0,1,2,3,4,5,6,7",
336 "EventCode": "0xA3",
339 "UMask": "0x5"
343 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3",
346 "EventCode": "0xA3",
349 "UMask": "0x14"
353 "Counter": "0,1,2,3",
354 "CounterHTOff": "0,1,2,3,4,5,6,7",
356 "EventCode": "0xA3",
359 "UMask": "0x4"
363 "Counter": "0,1,2,3",
364 "CounterHTOff": "0,1,2,3,4,5,6,7",
365 "EventCode": "0xA6",
369 "UMask": "0x2"
373 "Counter": "0,1,2,3",
374 "CounterHTOff": "0,1,2,3,4,5,6,7",
375 "EventCode": "0xA6",
379 "UMask": "0x4"
382 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
383 "Counter": "0,1,2,3",
384 "CounterHTOff": "0,1,2,3,4,5,6,7",
385 "EventCode": "0xA6",
386 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
387 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
389 "UMask": "0x8"
393 "Counter": "0,1,2,3",
394 "CounterHTOff": "0,1,2,3,4,5,6,7",
395 "EventCode": "0xA6",
399 "UMask": "0x10"
403 "Counter": "0,1,2,3",
404 "CounterHTOff": "0,1,2,3,4,5,6,7",
405 "EventCode": "0xA6",
408 "UMask": "0x40"
412 "Counter": "0,1,2,3",
413 "CounterHTOff": "0,1,2,3,4,5,6,7",
414 "EventCode": "0xA6",
418 "UMask": "0x1"
422 "Counter": "0,1,2,3",
423 "CounterHTOff": "0,1,2,3,4,5,6,7",
424 "EventCode": "0x87",
426 …0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the num…
428 "UMask": "0x1"
432 "Counter": "0,1,2,3",
433 "CounterHTOff": "0,1,2,3,4,5,6,7",
434 "EventCode": "0x55",
438 "UMask": "0x1"
442 "Counter": "Fixed counter 0",
443 "CounterHTOff": "Fixed counter 0",
445 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro…
447 "UMask": "0x1"
450 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
451 "Counter": "0,1,2,3",
452 "CounterHTOff": "0,1,2,3,4,5,6,7",
454 "EventCode": "0xC0",
456 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
461 "Counter": "0,1,2,3",
462 "CounterHTOff": "0,1,2,3,4,5,6,7",
464 "EventCode": "0xC0",
468 "UMask": "0x2"
475 "EventCode": "0xC0",
480 "UMask": "0x1"
484 "Counter": "0,2,3",
485 "CounterHTOff": "0,2,3",
488 "EventCode": "0xC0",
494 "UMask": "0x1"
497 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path …
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3,4,5,6,7",
500 "EventCode": "0x0D",
503 "UMask": "0x80"
507 "Counter": "0,1,2,3",
508 "CounterHTOff": "0,1,2,3,4,5,6,7",
509 "EventCode": "0x0D",
513 "UMask": "0x1"
518 "Counter": "0,1,2,3",
519 "CounterHTOff": "0,1,2,3,4,5,6,7",
520 "EventCode": "0x0D",
523 "UMask": "0x1"
527 "Counter": "0,1,2,3",
528 "CounterHTOff": "0,1,2,3,4,5,6,7",
529 "EventCode": "0x03",
533 "UMask": "0x8"
537 "Counter": "0,1,2,3",
538 "CounterHTOff": "0,1,2,3,4,5,6,7",
539 "EventCode": "0x03",
543 "UMask": "0x2"
547 "Counter": "0,1,2,3",
548 "CounterHTOff": "0,1,2,3,4,5,6,7",
549 "EventCode": "0x07",
553 "UMask": "0x1"
557 "Counter": "0,1,2,3",
558 "CounterHTOff": "0,1,2,3,4,5,6,7",
559 "EventCode": "0x4C",
561 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
563 "UMask": "0x1"
567 "Counter": "0,1,2,3",
568 "CounterHTOff": "0,1,2,3,4,5,6,7",
570 "EventCode": "0xA8",
572 …"PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector…
574 "UMask": "0x1"
578 "Counter": "0,1,2,3",
579 "CounterHTOff": "0,1,2,3,4,5,6,7",
581 "EventCode": "0xA8",
583 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
585 "UMask": "0x1"
589 "Counter": "0,1,2,3",
590 "CounterHTOff": "0,1,2,3,4,5,6,7",
591 "EventCode": "0xA8",
593 … "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
595 "UMask": "0x1"
599 "Counter": "0,1,2,3",
600 "CounterHTOff": "0,1,2,3,4,5,6,7",
603 "EventCode": "0xC3",
606 "UMask": "0x1"
609 "BriefDescription": "Self-modifying code (SMC) detected.",
610 "Counter": "0,1,2,3",
611 "CounterHTOff": "0,1,2,3,4,5,6,7",
612 "EventCode": "0xC3",
614 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
616 "UMask": "0x4"
619 …"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Exa…
620 "Counter": "0,1,2,3",
621 "CounterHTOff": "0,1,2,3,4,5,6,7",
622 "EventCode": "0xC1",
625 "UMask": "0x3f"
629 "Counter": "0,1,2,3",
630 "CounterHTOff": "0,1,2,3,4,5,6,7",
631 "EventCode": "0x59",
635 "UMask": "0x1"
638 "BriefDescription": "Resource-related stall cycles",
639 "Counter": "0,1,2,3",
640 "CounterHTOff": "0,1,2,3,4,5,6,7",
641 "EventCode": "0xa2",
643 "PublicDescription": "Counts resource-related stall cycles.",
645 "UMask": "0x1"
649 "Counter": "0,1,2,3",
650 "CounterHTOff": "0,1,2,3,4,5,6,7",
651 "EventCode": "0xA2",
653 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
655 "UMask": "0x8"
659 "Counter": "0,1,2,3",
660 "CounterHTOff": "0,1,2,3,4,5,6,7",
661 "EventCode": "0xCC",
665 "UMask": "0x20"
669 "Counter": "0,1,2,3",
670 "CounterHTOff": "0,1,2,3,4,5,6,7",
671 "EventCode": "0xCC",
674 "UMask": "0x40"
678 "Counter": "0,1,2,3",
679 "CounterHTOff": "0,1,2,3,4,5,6,7",
680 "EventCode": "0x5E",
682 …vation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. …
684 "UMask": "0x1"
688 "Counter": "0,1,2,3",
689 "CounterHTOff": "0,1,2,3,4,5,6,7",
692 "EventCode": "0x5E",
695 …eservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound iss…
697 "UMask": "0x1"
700 "BriefDescription": "Cycles per thread when uops are executed in port 0",
701 "Counter": "0,1,2,3",
702 "CounterHTOff": "0,1,2,3,4,5,6,7",
703 "EventCode": "0xA1",
705 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
707 "UMask": "0x1"
711 "Counter": "0,1,2,3",
712 "CounterHTOff": "0,1,2,3,4,5,6,7",
713 "EventCode": "0xA1",
715 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
717 "UMask": "0x2"
721 "Counter": "0,1,2,3",
722 "CounterHTOff": "0,1,2,3,4,5,6,7",
723 "EventCode": "0xA1",
725 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
727 "UMask": "0x4"
730 "BriefDescription": "Cycles per thread when uops are executed in port 3",
731 "Counter": "0,1,2,3",
732 "CounterHTOff": "0,1,2,3,4,5,6,7",
733 "EventCode": "0xA1",
735 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
737 "UMask": "0x8"
741 "Counter": "0,1,2,3",
742 "CounterHTOff": "0,1,2,3,4,5,6,7",
743 "EventCode": "0xA1",
745 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
747 "UMask": "0x10"
751 "Counter": "0,1,2,3",
752 "CounterHTOff": "0,1,2,3,4,5,6,7",
753 "EventCode": "0xA1",
755 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
757 "UMask": "0x20"
761 "Counter": "0,1,2,3",
762 "CounterHTOff": "0,1,2,3,4,5,6,7",
763 "EventCode": "0xA1",
765 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
767 "UMask": "0x40"
771 "Counter": "0,1,2,3",
772 "CounterHTOff": "0,1,2,3,4,5,6,7",
773 "EventCode": "0xA1",
775 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
777 "UMask": "0x80"
781 "Counter": "0,1,2,3",
782 "CounterHTOff": "0,1,2,3,4,5,6,7",
783 "EventCode": "0xB1",
787 "UMask": "0x2"
790 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
791 "Counter": "0,1,2,3",
792 "CounterHTOff": "0,1,2,3,4,5,6,7",
794 "EventCode": "0xB1",
797 "UMask": "0x2"
800 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
801 "Counter": "0,1,2,3",
802 "CounterHTOff": "0,1,2,3,4,5,6,7",
804 "EventCode": "0xB1",
807 "UMask": "0x2"
810 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
811 "Counter": "0,1,2,3",
812 "CounterHTOff": "0,1,2,3,4,5,6,7",
813 "CounterMask": "3",
814 "EventCode": "0xB1",
817 "UMask": "0x2"
820 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
821 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7",
824 "EventCode": "0xB1",
827 "UMask": "0x2"
830 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
831 "Counter": "0,1,2,3",
832 "CounterHTOff": "0,1,2,3,4,5,6,7",
834 "EventCode": "0xB1",
838 "UMask": "0x2"
841 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3,4,5,6,7",
845 "EventCode": "0xB1",
847 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
849 "UMask": "0x1"
852 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
856 "EventCode": "0xB1",
858 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
860 "UMask": "0x1"
863 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
864 "Counter": "0,1,2,3",
865 "CounterHTOff": "0,1,2,3,4,5,6,7",
866 "CounterMask": "3",
867 "EventCode": "0xB1",
869 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
871 "UMask": "0x1"
874 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
875 "Counter": "0,1,2,3",
876 "CounterHTOff": "0,1,2,3,4,5,6,7",
878 "EventCode": "0xB1",
880 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
882 "UMask": "0x1"
886 "Counter": "0,1,2,3",
887 "CounterHTOff": "0,1,2,3,4,5,6,7",
889 "EventCode": "0xB1",
894 "UMask": "0x1"
897 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7",
900 "EventCode": "0xB1",
902 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
904 "UMask": "0x1"
908 "Counter": "0,1,2,3",
909 "CounterHTOff": "0,1,2,3,4,5,6,7",
910 "EventCode": "0xB1",
914 "UMask": "0x10"
918 "Counter": "0,1,2,3",
919 "CounterHTOff": "0,1,2,3,4,5,6,7",
920 "EventCode": "0x0E",
924 "UMask": "0x1"
927 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
928 "Counter": "0,1,2,3",
929 "CounterHTOff": "0,1,2,3,4,5,6,7",
930 "EventCode": "0x0E",
933 "UMask": "0x20"
937 "Counter": "0,1,2,3",
938 "CounterHTOff": "0,1,2,3,4,5,6,7",
940 "EventCode": "0x0E",
945 "UMask": "0x1"
948 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
949 "Counter": "0,1,2,3",
950 "CounterHTOff": "0,1,2,3,4,5,6,7",
951 "EventCode": "0x0E",
953 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
955 "UMask": "0x2"
958 "BriefDescription": "Number of macro-fused uops retired. (non precise)",
959 "Counter": "0,1,2,3",
960 "CounterHTOff": "0,1,2,3,4,5,6,7",
961 "EventCode": "0xc2",
963 "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
965 "UMask": "0x4"
969 "Counter": "0,1,2,3",
970 "CounterHTOff": "0,1,2,3,4,5,6,7",
971 "EventCode": "0xC2",
975 "UMask": "0x2"
979 "Counter": "0,1,2,3",
980 "CounterHTOff": "0,1,2,3,4,5,6,7",
982 "EventCode": "0xC2",
987 "UMask": "0x2"
991 "Counter": "0,1,2,3",
992 "CounterHTOff": "0,1,2,3,4,5,6,7",
994 "EventCode": "0xC2",
999 "UMask": "0x2"