Lines Matching +full:3 +full:- +full:line
3 "BriefDescription": "L1D data line replacements",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 … "Counts L1D data line replacements including opportunistic replacements, and replacements that re…
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
34 "Counter": "0,1,2,3",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "Counter": "0,1,2,3",
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
76 "Counter": "0,1,2,3",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 "Counter": "0,1,2,3",
86 "CounterHTOff": "0,1,2,3,4,5,6,7",
94 "Counter": "0,1,2,3",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
114 "Counter": "0,1,2,3",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
124 "Counter": "0,1,2,3",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
134 "Counter": "0,1,2,3",
135 "CounterHTOff": "0,1,2,3,4,5,6,7",
144 "Counter": "0,1,2,3",
145 "CounterHTOff": "0,1,2,3,4,5,6,7",
154 "Counter": "0,1,2,3",
155 "CounterHTOff": "0,1,2,3,4,5,6,7",
164 "Counter": "0,1,2,3",
165 "CounterHTOff": "0,1,2,3,4,5,6,7",
174 "Counter": "0,1,2,3",
175 "CounterHTOff": "0,1,2,3,4,5,6,7",
184 "Counter": "0,1,2,3",
185 "CounterHTOff": "0,1,2,3,4,5,6,7",
194 "Counter": "0,1,2,3",
195 "CounterHTOff": "0,1,2,3,4,5,6,7",
204 "Counter": "0,1,2,3",
205 "CounterHTOff": "0,1,2,3,4,5,6,7",
214 "Counter": "0,1,2,3",
215 "CounterHTOff": "0,1,2,3,4,5,6,7",
224 "Counter": "0,1,2,3",
225 "CounterHTOff": "0,1,2,3,4,5,6,7",
234 "Counter": "0,1,2,3",
235 "CounterHTOff": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3",
245 "CounterHTOff": "0,1,2,3,4,5,6,7",
248 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
254 "Counter": "0,1,2,3",
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
258 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
264 "Counter": "0,1,2,3",
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
273 "BriefDescription": "Core-originated cacheable demand requests missed L3",
274 "Counter": "0,1,2,3",
275 "CounterHTOff": "0,1,2,3,4,5,6,7",
279 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
284 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
285 "Counter": "0,1,2,3",
286 "CounterHTOff": "0,1,2,3,4,5,6,7",
290 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests …
296 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3",
307 "Counter": "0,1,2,3",
308 "CounterHTOff": "0,1,2,3",
319 "Counter": "0,1,2,3",
320 "CounterHTOff": "0,1,2,3",
326 "PublicDescription": "Counts all retired memory instructions - loads and stores.",
332 "Counter": "0,1,2,3",
333 "CounterHTOff": "0,1,2,3",
343 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3",
355 "Counter": "0,1,2,3",
356 "CounterHTOff": "0,1,2,3",
368 "Counter": "0,1,2,3",
369 "CounterHTOff": "0,1,2,3",
374 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
380 "Counter": "0,1,2,3",
381 "CounterHTOff": "0,1,2,3",
387 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
392 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
393 "Counter": "0,1,2,3",
394 "CounterHTOff": "0,1,2,3",
399 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
405 "Counter": "0,1,2,3",
406 "CounterHTOff": "0,1,2,3",
416 …tired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core …
417 "Counter": "0,1,2,3",
418 "CounterHTOff": "0,1,2,3",
428 "Counter": "0,1,2,3",
429 "CounterHTOff": "0,1,2,3",
440 "Counter": "0,1,2,3",
441 "CounterHTOff": "0,1,2,3",
452 "Counter": "0,1,2,3",
453 "CounterHTOff": "0,1,2,3",
463 "Counter": "0,1,2,3",
464 "CounterHTOff": "0,1,2,3",
475 "Counter": "0,1,2,3",
476 "CounterHTOff": "0,1,2,3",
487 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3",
497 …es were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready…
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3",
504 …d in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready…
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3",
522 "Counter": "0,1,2,3",
523 "CounterHTOff": "0,1,2,3",
534 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3",
546 "Counter": "0,1,2,3",
547 "CounterHTOff": "0,1,2,3",
558 "Counter": "0,1,2,3",
559 "CounterHTOff": "0,1,2,3",
570 "Counter": "0,1,2,3",
571 "CounterHTOff": "0,1,2,3",
582 "Counter": "0,1,2,3",
583 "CounterHTOff": "0,1,2,3,4,5,6,7",
592 "Counter": "0,1,2,3",
593 "CounterHTOff": "0,1,2,3,4,5,6,7",
602 "Counter": "0,1,2,3",
603 "CounterHTOff": "0,1,2,3,4,5,6,7",
606 "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
612 "Counter": "0,1,2,3",
613 "CounterHTOff": "0,1,2,3,4,5,6,7",
622 "Counter": "0,1,2,3",
623 "CounterHTOff": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3",
633 "CounterHTOff": "0,1,2,3,4,5,6,7",
642 "Counter": "0,1,2,3",
643 "CounterHTOff": "0,1,2,3,4,5,6,7",
646 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
652 "Counter": "0,1,2,3",
653 "CounterHTOff": "0,1,2,3,4,5,6,7",
657 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
663 "Counter": "0,1,2,3",
664 "CounterHTOff": "0,1,2,3,4,5,6,7",
674 "Counter": "0,1,2,3",
675 "CounterHTOff": "0,1,2,3,4,5,6,7",
679 …utstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
685 "Counter": "0,1,2,3",
686 "CounterHTOff": "0,1,2,3,4,5,6,7",
696 "Counter": "0,1,2,3",
697 "CounterHTOff": "0,1,2,3,4,5,6,7",
706 "Counter": "0,1,2,3",
707 "CounterHTOff": "0,1,2,3,4,5,6,7",
716 "Counter": "0,1,2,3",
717 "CounterHTOff": "0,1,2,3,4,5,6,7",
726 "Counter": "0,1,2,3",
727 "CounterHTOff": "0,1,2,3,4,5,6,7",
730 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
736 "Counter": "0,1,2,3",
737 "CounterHTOff": "0,1,2,3",
746 "Counter": "0,1,2,3",
747 "CounterHTOff": "0,1,2,3",
758 "Counter": "0,1,2,3",
759 "CounterHTOff": "0,1,2,3",
769 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
770 "Counter": "0,1,2,3",
771 "CounterHTOff": "0,1,2,3",
781 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
782 "Counter": "0,1,2,3",
783 "CounterHTOff": "0,1,2,3",
793 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3",
806 "Counter": "0,1,2,3",
807 "CounterHTOff": "0,1,2,3",
818 "Counter": "0,1,2,3",
819 "CounterHTOff": "0,1,2,3",
830 "Counter": "0,1,2,3",
831 "CounterHTOff": "0,1,2,3",
841 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3",
853 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
854 "Counter": "0,1,2,3",
855 "CounterHTOff": "0,1,2,3",
865 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
866 "Counter": "0,1,2,3",
867 "CounterHTOff": "0,1,2,3",
878 "Counter": "0,1,2,3",
879 "CounterHTOff": "0,1,2,3",
890 "Counter": "0,1,2,3",
891 "CounterHTOff": "0,1,2,3",
902 "Counter": "0,1,2,3",
903 "CounterHTOff": "0,1,2,3",
913 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
914 "Counter": "0,1,2,3",
915 "CounterHTOff": "0,1,2,3",
925 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
926 "Counter": "0,1,2,3",
927 "CounterHTOff": "0,1,2,3",
937 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
938 "Counter": "0,1,2,3",
939 "CounterHTOff": "0,1,2,3",
950 "Counter": "0,1,2,3",
951 "CounterHTOff": "0,1,2,3",
962 "Counter": "0,1,2,3",
963 "CounterHTOff": "0,1,2,3",
974 "Counter": "0,1,2,3",
975 "CounterHTOff": "0,1,2,3",
985 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
986 "Counter": "0,1,2,3",
987 "CounterHTOff": "0,1,2,3",
997 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
998 "Counter": "0,1,2,3",
999 "CounterHTOff": "0,1,2,3",
1009 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1010 "Counter": "0,1,2,3",
1011 "CounterHTOff": "0,1,2,3",
1022 "Counter": "0,1,2,3",
1023 "CounterHTOff": "0,1,2,3",
1034 "Counter": "0,1,2,3",
1035 "CounterHTOff": "0,1,2,3",
1046 "Counter": "0,1,2,3",
1047 "CounterHTOff": "0,1,2,3",
1057 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1058 "Counter": "0,1,2,3",
1059 "CounterHTOff": "0,1,2,3",
1069 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1070 "Counter": "0,1,2,3",
1071 "CounterHTOff": "0,1,2,3",
1081 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1082 "Counter": "0,1,2,3",
1083 "CounterHTOff": "0,1,2,3",
1094 "Counter": "0,1,2,3",
1095 "CounterHTOff": "0,1,2,3",
1106 "Counter": "0,1,2,3",
1107 "CounterHTOff": "0,1,2,3",
1118 "Counter": "0,1,2,3",
1119 "CounterHTOff": "0,1,2,3",
1129 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1130 "Counter": "0,1,2,3",
1131 "CounterHTOff": "0,1,2,3",
1141 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1142 "Counter": "0,1,2,3",
1143 "CounterHTOff": "0,1,2,3",
1153 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1154 "Counter": "0,1,2,3",
1155 "CounterHTOff": "0,1,2,3",
1166 "Counter": "0,1,2,3",
1167 "CounterHTOff": "0,1,2,3",
1178 "Counter": "0,1,2,3",
1179 "CounterHTOff": "0,1,2,3",
1190 "Counter": "0,1,2,3",
1191 "CounterHTOff": "0,1,2,3",
1201 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1202 "Counter": "0,1,2,3",
1203 "CounterHTOff": "0,1,2,3",
1213 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1214 "Counter": "0,1,2,3",
1215 "CounterHTOff": "0,1,2,3",
1225 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1226 "Counter": "0,1,2,3",
1227 "CounterHTOff": "0,1,2,3",
1238 "Counter": "0,1,2,3",
1239 "CounterHTOff": "0,1,2,3",
1250 "Counter": "0,1,2,3",
1251 "CounterHTOff": "0,1,2,3",
1262 "Counter": "0,1,2,3",
1263 "CounterHTOff": "0,1,2,3",
1273 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1274 "Counter": "0,1,2,3",
1275 "CounterHTOff": "0,1,2,3",
1285 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1286 "Counter": "0,1,2,3",
1287 "CounterHTOff": "0,1,2,3",
1297 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1298 "Counter": "0,1,2,3",
1299 "CounterHTOff": "0,1,2,3",
1310 "Counter": "0,1,2,3",
1311 "CounterHTOff": "0,1,2,3",
1322 "Counter": "0,1,2,3",
1323 "CounterHTOff": "0,1,2,3",
1334 "Counter": "0,1,2,3",
1335 "CounterHTOff": "0,1,2,3",
1345 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1346 "Counter": "0,1,2,3",
1347 "CounterHTOff": "0,1,2,3",
1357 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1358 "Counter": "0,1,2,3",
1359 "CounterHTOff": "0,1,2,3",
1369 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1370 "Counter": "0,1,2,3",
1371 "CounterHTOff": "0,1,2,3",
1382 "Counter": "0,1,2,3",
1383 "CounterHTOff": "0,1,2,3",
1394 "Counter": "0,1,2,3",
1395 "CounterHTOff": "0,1,2,3",
1406 "Counter": "0,1,2,3",
1407 "CounterHTOff": "0,1,2,3",
1417 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1418 "Counter": "0,1,2,3",
1419 "CounterHTOff": "0,1,2,3",
1429 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1430 "Counter": "0,1,2,3",
1431 "CounterHTOff": "0,1,2,3",
1441 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1442 "Counter": "0,1,2,3",
1443 "CounterHTOff": "0,1,2,3",
1454 "Counter": "0,1,2,3",
1455 "CounterHTOff": "0,1,2,3",
1466 "Counter": "0,1,2,3",
1467 "CounterHTOff": "0,1,2,3",
1478 "Counter": "0,1,2,3",
1479 "CounterHTOff": "0,1,2,3",
1489 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1490 "Counter": "0,1,2,3",
1491 "CounterHTOff": "0,1,2,3",
1501 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1502 "Counter": "0,1,2,3",
1503 "CounterHTOff": "0,1,2,3",
1513 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1514 "Counter": "0,1,2,3",
1515 "CounterHTOff": "0,1,2,3",
1526 "Counter": "0,1,2,3",
1527 "CounterHTOff": "0,1,2,3",
1538 "Counter": "0,1,2,3",
1539 "CounterHTOff": "0,1,2,3",
1550 "Counter": "0,1,2,3",
1551 "CounterHTOff": "0,1,2,3",
1561 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1562 "Counter": "0,1,2,3",
1563 "CounterHTOff": "0,1,2,3",
1573 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1574 "Counter": "0,1,2,3",
1575 "CounterHTOff": "0,1,2,3",
1585 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1586 "Counter": "0,1,2,3",
1587 "CounterHTOff": "0,1,2,3",
1598 "Counter": "0,1,2,3",
1599 "CounterHTOff": "0,1,2,3",
1609 "BriefDescription": "Number of cache line split locks sent to uncore.",
1610 "Counter": "0,1,2,3",
1611 "CounterHTOff": "0,1,2,3,4,5,6,7",
1614 "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
1620 "Counter": "0,1,2,3",
1621 "CounterHTOff": "0,1,2,3,4,5,6,7",
1629 "Counter": "0,1,2,3",
1630 "CounterHTOff": "0,1,2,3,4,5,6,7",
1638 "Counter": "0,1,2,3",
1639 "CounterHTOff": "0,1,2,3,4,5,6,7",
1647 "Counter": "0,1,2,3",
1648 "CounterHTOff": "0,1,2,3,4,5,6,7",