Lines Matching +full:0 +full:- +full:3
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
6 "EventCode": "0x51",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
10 "UMask": "0x1"
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "EventCode": "0x48",
20 "UMask": "0x2"
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
26 "EventCode": "0x48",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
30 "UMask": "0x1"
34 "Counter": "0,1,2,3",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
37 "EventCode": "0x48",
41 "UMask": "0x1"
46 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
49 "EventCode": "0x48",
52 "UMask": "0x1"
56 "Counter": "0,1,2,3",
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 "EventCode": "0xF1",
62 "UMask": "0x1f"
66 "Counter": "0,1,2,3",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
68 "EventCode": "0xF2",
72 "UMask": "0x2"
75 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
76 "Counter": "0,1,2,3",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
78 "EventCode": "0xF2",
81 "UMask": "0x1"
85 "Counter": "0,1,2,3",
86 "CounterHTOff": "0,1,2,3,4,5,6,7",
87 "EventCode": "0xF2",
90 "UMask": "0x4"
94 "Counter": "0,1,2,3",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "EventCode": "0xF2",
100 "UMask": "0x4"
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
106 "EventCode": "0x24",
110 "UMask": "0xe4"
114 "Counter": "0,1,2,3",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
116 "EventCode": "0x24",
120 "UMask": "0xe1"
124 "Counter": "0,1,2,3",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
126 "EventCode": "0x24",
130 "UMask": "0x27"
134 "Counter": "0,1,2,3",
135 "CounterHTOff": "0,1,2,3,4,5,6,7",
136 "EventCode": "0x24",
140 "UMask": "0xe7"
144 "Counter": "0,1,2,3",
145 "CounterHTOff": "0,1,2,3,4,5,6,7",
146 "EventCode": "0x24",
150 "UMask": "0xf8"
154 "Counter": "0,1,2,3",
155 "CounterHTOff": "0,1,2,3,4,5,6,7",
156 "EventCode": "0x24",
160 "UMask": "0xe2"
164 "Counter": "0,1,2,3",
165 "CounterHTOff": "0,1,2,3,4,5,6,7",
166 "EventCode": "0x24",
170 "UMask": "0xc4"
174 "Counter": "0,1,2,3",
175 "CounterHTOff": "0,1,2,3,4,5,6,7",
176 "EventCode": "0x24",
180 "UMask": "0x24"
184 "Counter": "0,1,2,3",
185 "CounterHTOff": "0,1,2,3,4,5,6,7",
186 "EventCode": "0x24",
190 "UMask": "0xc1"
194 "Counter": "0,1,2,3",
195 "CounterHTOff": "0,1,2,3,4,5,6,7",
196 "EventCode": "0x24",
200 "UMask": "0x21"
204 "Counter": "0,1,2,3",
205 "CounterHTOff": "0,1,2,3,4,5,6,7",
206 "EventCode": "0x24",
210 "UMask": "0x3f"
214 "Counter": "0,1,2,3",
215 "CounterHTOff": "0,1,2,3,4,5,6,7",
216 "EventCode": "0x24",
220 "UMask": "0xd8"
224 "Counter": "0,1,2,3",
225 "CounterHTOff": "0,1,2,3,4,5,6,7",
226 "EventCode": "0x24",
230 "UMask": "0x38"
234 "Counter": "0,1,2,3",
235 "CounterHTOff": "0,1,2,3,4,5,6,7",
236 "EventCode": "0x24",
240 "UMask": "0xff"
244 "Counter": "0,1,2,3",
245 "CounterHTOff": "0,1,2,3,4,5,6,7",
246 "EventCode": "0x24",
248 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
250 "UMask": "0xc2"
254 "Counter": "0,1,2,3",
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
256 "EventCode": "0x24",
258 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
260 "UMask": "0x22"
264 "Counter": "0,1,2,3",
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
266 "EventCode": "0xF0",
270 "UMask": "0x40"
273 "BriefDescription": "Core-originated cacheable demand requests missed L3",
274 "Counter": "0,1,2,3",
275 "CounterHTOff": "0,1,2,3,4,5,6,7",
277 "EventCode": "0x2E",
279 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
281 "UMask": "0x41"
284 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
285 "Counter": "0,1,2,3",
286 "CounterHTOff": "0,1,2,3,4,5,6,7",
288 "EventCode": "0x2E",
290 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests …
292 "UMask": "0x4f"
296 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3",
299 "EventCode": "0xD0",
303 "UMask": "0x81"
307 "Counter": "0,1,2,3",
308 "CounterHTOff": "0,1,2,3",
310 "EventCode": "0xD0",
315 "UMask": "0x82"
319 "Counter": "0,1,2,3",
320 "CounterHTOff": "0,1,2,3",
322 "EventCode": "0xD0",
326 "PublicDescription": "Counts all retired memory instructions - loads and stores.",
328 "UMask": "0x83"
332 "Counter": "0,1,2,3",
333 "CounterHTOff": "0,1,2,3",
335 "EventCode": "0xD0",
339 "UMask": "0x21"
343 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3",
346 "EventCode": "0xD0",
351 "UMask": "0x41"
355 "Counter": "0,1,2,3",
356 "CounterHTOff": "0,1,2,3",
358 "EventCode": "0xD0",
364 "UMask": "0x42"
368 "Counter": "0,1,2,3",
369 "CounterHTOff": "0,1,2,3",
371 "EventCode": "0xD0",
374 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
376 "UMask": "0x11"
380 "Counter": "0,1,2,3",
381 "CounterHTOff": "0,1,2,3",
383 "EventCode": "0xD0",
387 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
389 "UMask": "0x12"
392 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
393 "Counter": "0,1,2,3",
394 "CounterHTOff": "0,1,2,3",
396 "EventCode": "0xD2",
399 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
401 "UMask": "0x2"
405 "Counter": "0,1,2,3",
406 "CounterHTOff": "0,1,2,3",
408 "EventCode": "0xD2",
413 "UMask": "0x4"
416 …tired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core …
417 "Counter": "0,1,2,3",
418 "CounterHTOff": "0,1,2,3",
420 "EventCode": "0xD2",
424 "UMask": "0x1"
428 "Counter": "0,1,2,3",
429 "CounterHTOff": "0,1,2,3",
431 "EventCode": "0xD2",
436 "UMask": "0x8"
440 "Counter": "0,1,2,3",
441 "CounterHTOff": "0,1,2,3",
443 "EventCode": "0xD3",
448 "UMask": "0x1"
452 "Counter": "0,1,2,3",
453 "CounterHTOff": "0,1,2,3",
455 "EventCode": "0xD3",
459 "UMask": "0x2"
463 "Counter": "0,1,2,3",
464 "CounterHTOff": "0,1,2,3",
466 "EventCode": "0xD3",
471 "UMask": "0x8"
475 "Counter": "0,1,2,3",
476 "CounterHTOff": "0,1,2,3",
478 "EventCode": "0xD3",
483 "UMask": "0x4"
487 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3",
490 "EventCode": "0xD4",
494 "UMask": "0x4"
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3",
501 "EventCode": "0xD1",
506 "UMask": "0x40"
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3",
513 "EventCode": "0xD1",
518 "UMask": "0x1"
522 "Counter": "0,1,2,3",
523 "CounterHTOff": "0,1,2,3",
525 "EventCode": "0xD1",
530 "UMask": "0x8"
534 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3",
537 "EventCode": "0xD1",
542 "UMask": "0x2"
546 "Counter": "0,1,2,3",
547 "CounterHTOff": "0,1,2,3",
549 "EventCode": "0xD1",
554 "UMask": "0x10"
558 "Counter": "0,1,2,3",
559 "CounterHTOff": "0,1,2,3",
561 "EventCode": "0xD1",
566 "UMask": "0x4"
570 "Counter": "0,1,2,3",
571 "CounterHTOff": "0,1,2,3",
573 "EventCode": "0xD1",
578 "UMask": "0x20"
582 "Counter": "0,1,2,3",
583 "CounterHTOff": "0,1,2,3,4,5,6,7",
584 "EventCode": "0xB0",
588 "UMask": "0x8"
592 "Counter": "0,1,2,3",
593 "CounterHTOff": "0,1,2,3,4,5,6,7",
594 "EventCode": "0xB0",
598 "UMask": "0x80"
602 "Counter": "0,1,2,3",
603 "CounterHTOff": "0,1,2,3,4,5,6,7",
604 "EventCode": "0xB0",
606 "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
608 "UMask": "0x2"
612 "Counter": "0,1,2,3",
613 "CounterHTOff": "0,1,2,3,4,5,6,7",
614 "EventCode": "0xB0",
618 "UMask": "0x1"
622 "Counter": "0,1,2,3",
623 "CounterHTOff": "0,1,2,3,4,5,6,7",
624 "EventCode": "0xB0",
628 "UMask": "0x4"
632 "Counter": "0,1,2,3",
633 "CounterHTOff": "0,1,2,3,4,5,6,7",
634 "EventCode": "0xB2",
638 "UMask": "0x1"
642 "Counter": "0,1,2,3",
643 "CounterHTOff": "0,1,2,3,4,5,6,7",
644 "EventCode": "0x60",
646 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
648 "UMask": "0x8"
652 "Counter": "0,1,2,3",
653 "CounterHTOff": "0,1,2,3,4,5,6,7",
655 "EventCode": "0x60",
657 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
659 "UMask": "0x8"
663 "Counter": "0,1,2,3",
664 "CounterHTOff": "0,1,2,3,4,5,6,7",
666 "EventCode": "0x60",
670 "UMask": "0x2"
674 "Counter": "0,1,2,3",
675 "CounterHTOff": "0,1,2,3,4,5,6,7",
677 "EventCode": "0x60",
679 …utstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
681 "UMask": "0x1"
685 "Counter": "0,1,2,3",
686 "CounterHTOff": "0,1,2,3,4,5,6,7",
688 "EventCode": "0x60",
692 "UMask": "0x4"
696 "Counter": "0,1,2,3",
697 "CounterHTOff": "0,1,2,3,4,5,6,7",
698 "EventCode": "0x60",
702 "UMask": "0x2"
706 "Counter": "0,1,2,3",
707 "CounterHTOff": "0,1,2,3,4,5,6,7",
708 "EventCode": "0x60",
712 "UMask": "0x1"
716 "Counter": "0,1,2,3",
717 "CounterHTOff": "0,1,2,3,4,5,6,7",
719 "EventCode": "0x60",
722 "UMask": "0x1"
726 "Counter": "0,1,2,3",
727 "CounterHTOff": "0,1,2,3,4,5,6,7",
728 "EventCode": "0x60",
730 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
732 "UMask": "0x4"
736 "Counter": "0,1,2,3",
737 "CounterHTOff": "0,1,2,3",
738 "EventCode": "0xB7, 0xBB",
742 "UMask": "0x1"
746 "Counter": "0,1,2,3",
747 "CounterHTOff": "0,1,2,3",
748 "EventCode": "0xB7, 0xBB",
750 "MSRIndex": "0x1a6,0x1a7",
751 "MSRValue": "0x10491",
754 "UMask": "0x1"
758 "Counter": "0,1,2,3",
759 "CounterHTOff": "0,1,2,3",
760 "EventCode": "0xB7, 0xBB",
762 "MSRIndex": "0x1a6,0x1a7",
763 "MSRValue": "0x3F803C0491",
766 "UMask": "0x1"
770 "Counter": "0,1,2,3",
771 "CounterHTOff": "0,1,2,3",
772 "EventCode": "0xB7, 0xBB",
774 "MSRIndex": "0x1a6,0x1a7",
775 "MSRValue": "0x10003C0491",
778 "UMask": "0x1"
782 "Counter": "0,1,2,3",
783 "CounterHTOff": "0,1,2,3",
784 "EventCode": "0xB7, 0xBB",
786 "MSRIndex": "0x1a6,0x1a7",
787 "MSRValue": "0x4003C0491",
790 "UMask": "0x1"
793 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3",
796 "EventCode": "0xB7, 0xBB",
798 "MSRIndex": "0x1a6,0x1a7",
799 "MSRValue": "0x1003C0491",
802 "UMask": "0x1"
806 "Counter": "0,1,2,3",
807 "CounterHTOff": "0,1,2,3",
808 "EventCode": "0xB7, 0xBB",
810 "MSRIndex": "0x1a6,0x1a7",
811 "MSRValue": "0x8003C0491",
814 "UMask": "0x1"
818 "Counter": "0,1,2,3",
819 "CounterHTOff": "0,1,2,3",
820 "EventCode": "0xB7, 0xBB",
822 "MSRIndex": "0x1a6,0x1a7",
823 "MSRValue": "0x10490",
826 "UMask": "0x1"
830 "Counter": "0,1,2,3",
831 "CounterHTOff": "0,1,2,3",
832 "EventCode": "0xB7, 0xBB",
834 "MSRIndex": "0x1a6,0x1a7",
835 "MSRValue": "0x3F803C0490",
838 "UMask": "0x1"
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3",
844 "EventCode": "0xB7, 0xBB",
846 "MSRIndex": "0x1a6,0x1a7",
847 "MSRValue": "0x10003C0490",
850 "UMask": "0x1"
854 "Counter": "0,1,2,3",
855 "CounterHTOff": "0,1,2,3",
856 "EventCode": "0xB7, 0xBB",
858 "MSRIndex": "0x1a6,0x1a7",
859 "MSRValue": "0x4003C0490",
862 "UMask": "0x1"
865 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
866 "Counter": "0,1,2,3",
867 "CounterHTOff": "0,1,2,3",
868 "EventCode": "0xB7, 0xBB",
870 "MSRIndex": "0x1a6,0x1a7",
871 "MSRValue": "0x1003C0490",
874 "UMask": "0x1"
878 "Counter": "0,1,2,3",
879 "CounterHTOff": "0,1,2,3",
880 "EventCode": "0xB7, 0xBB",
882 "MSRIndex": "0x1a6,0x1a7",
883 "MSRValue": "0x8003C0490",
886 "UMask": "0x1"
890 "Counter": "0,1,2,3",
891 "CounterHTOff": "0,1,2,3",
892 "EventCode": "0xB7, 0xBB",
894 "MSRIndex": "0x1a6,0x1a7",
895 "MSRValue": "0x10120",
898 "UMask": "0x1"
902 "Counter": "0,1,2,3",
903 "CounterHTOff": "0,1,2,3",
904 "EventCode": "0xB7, 0xBB",
906 "MSRIndex": "0x1a6,0x1a7",
907 "MSRValue": "0x3F803C0120",
910 "UMask": "0x1"
914 "Counter": "0,1,2,3",
915 "CounterHTOff": "0,1,2,3",
916 "EventCode": "0xB7, 0xBB",
918 "MSRIndex": "0x1a6,0x1a7",
919 "MSRValue": "0x10003C0120",
922 "UMask": "0x1"
926 "Counter": "0,1,2,3",
927 "CounterHTOff": "0,1,2,3",
928 "EventCode": "0xB7, 0xBB",
930 "MSRIndex": "0x1a6,0x1a7",
931 "MSRValue": "0x4003C0120",
934 "UMask": "0x1"
937 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
938 "Counter": "0,1,2,3",
939 "CounterHTOff": "0,1,2,3",
940 "EventCode": "0xB7, 0xBB",
942 "MSRIndex": "0x1a6,0x1a7",
943 "MSRValue": "0x1003C0120",
946 "UMask": "0x1"
950 "Counter": "0,1,2,3",
951 "CounterHTOff": "0,1,2,3",
952 "EventCode": "0xB7, 0xBB",
954 "MSRIndex": "0x1a6,0x1a7",
955 "MSRValue": "0x8003C0120",
958 "UMask": "0x1"
962 "Counter": "0,1,2,3",
963 "CounterHTOff": "0,1,2,3",
964 "EventCode": "0xB7, 0xBB",
966 "MSRIndex": "0x1a6,0x1a7",
967 "MSRValue": "0x10122",
970 "UMask": "0x1"
974 "Counter": "0,1,2,3",
975 "CounterHTOff": "0,1,2,3",
976 "EventCode": "0xB7, 0xBB",
978 "MSRIndex": "0x1a6,0x1a7",
979 "MSRValue": "0x3F803C0122",
982 "UMask": "0x1"
986 "Counter": "0,1,2,3",
987 "CounterHTOff": "0,1,2,3",
988 "EventCode": "0xB7, 0xBB",
990 "MSRIndex": "0x1a6,0x1a7",
991 "MSRValue": "0x10003C0122",
994 "UMask": "0x1"
998 "Counter": "0,1,2,3",
999 "CounterHTOff": "0,1,2,3",
1000 "EventCode": "0xB7, 0xBB",
1002 "MSRIndex": "0x1a6,0x1a7",
1003 "MSRValue": "0x4003C0122",
1006 "UMask": "0x1"
1009 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1010 "Counter": "0,1,2,3",
1011 "CounterHTOff": "0,1,2,3",
1012 "EventCode": "0xB7, 0xBB",
1014 "MSRIndex": "0x1a6,0x1a7",
1015 "MSRValue": "0x1003C0122",
1018 "UMask": "0x1"
1022 "Counter": "0,1,2,3",
1023 "CounterHTOff": "0,1,2,3",
1024 "EventCode": "0xB7, 0xBB",
1026 "MSRIndex": "0x1a6,0x1a7",
1027 "MSRValue": "0x8003C0122",
1030 "UMask": "0x1"
1034 "Counter": "0,1,2,3",
1035 "CounterHTOff": "0,1,2,3",
1036 "EventCode": "0xB7, 0xBB",
1038 "MSRIndex": "0x1a6,0x1a7",
1039 "MSRValue": "0x10004",
1042 "UMask": "0x1"
1046 "Counter": "0,1,2,3",
1047 "CounterHTOff": "0,1,2,3",
1048 "EventCode": "0xB7, 0xBB",
1050 "MSRIndex": "0x1a6,0x1a7",
1051 "MSRValue": "0x3F803C0004",
1054 "UMask": "0x1"
1058 "Counter": "0,1,2,3",
1059 "CounterHTOff": "0,1,2,3",
1060 "EventCode": "0xB7, 0xBB",
1062 "MSRIndex": "0x1a6,0x1a7",
1063 "MSRValue": "0x10003C0004",
1066 "UMask": "0x1"
1070 "Counter": "0,1,2,3",
1071 "CounterHTOff": "0,1,2,3",
1072 "EventCode": "0xB7, 0xBB",
1074 "MSRIndex": "0x1a6,0x1a7",
1075 "MSRValue": "0x4003C0004",
1078 "UMask": "0x1"
1081 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1082 "Counter": "0,1,2,3",
1083 "CounterHTOff": "0,1,2,3",
1084 "EventCode": "0xB7, 0xBB",
1086 "MSRIndex": "0x1a6,0x1a7",
1087 "MSRValue": "0x1003C0004",
1090 "UMask": "0x1"
1094 "Counter": "0,1,2,3",
1095 "CounterHTOff": "0,1,2,3",
1096 "EventCode": "0xB7, 0xBB",
1098 "MSRIndex": "0x1a6,0x1a7",
1099 "MSRValue": "0x8003C0004",
1102 "UMask": "0x1"
1106 "Counter": "0,1,2,3",
1107 "CounterHTOff": "0,1,2,3",
1108 "EventCode": "0xB7, 0xBB",
1110 "MSRIndex": "0x1a6,0x1a7",
1111 "MSRValue": "0x10001",
1114 "UMask": "0x1"
1118 "Counter": "0,1,2,3",
1119 "CounterHTOff": "0,1,2,3",
1120 "EventCode": "0xB7, 0xBB",
1122 "MSRIndex": "0x1a6,0x1a7",
1123 "MSRValue": "0x3F803C0001",
1126 "UMask": "0x1"
1130 "Counter": "0,1,2,3",
1131 "CounterHTOff": "0,1,2,3",
1132 "EventCode": "0xB7, 0xBB",
1134 "MSRIndex": "0x1a6,0x1a7",
1135 "MSRValue": "0x10003C0001",
1138 "UMask": "0x1"
1142 "Counter": "0,1,2,3",
1143 "CounterHTOff": "0,1,2,3",
1144 "EventCode": "0xB7, 0xBB",
1146 "MSRIndex": "0x1a6,0x1a7",
1147 "MSRValue": "0x4003C0001",
1150 "UMask": "0x1"
1153 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1154 "Counter": "0,1,2,3",
1155 "CounterHTOff": "0,1,2,3",
1156 "EventCode": "0xB7, 0xBB",
1158 "MSRIndex": "0x1a6,0x1a7",
1159 "MSRValue": "0x1003C0001",
1162 "UMask": "0x1"
1166 "Counter": "0,1,2,3",
1167 "CounterHTOff": "0,1,2,3",
1168 "EventCode": "0xB7, 0xBB",
1170 "MSRIndex": "0x1a6,0x1a7",
1171 "MSRValue": "0x8003C0001",
1174 "UMask": "0x1"
1178 "Counter": "0,1,2,3",
1179 "CounterHTOff": "0,1,2,3",
1180 "EventCode": "0xB7, 0xBB",
1182 "MSRIndex": "0x1a6,0x1a7",
1183 "MSRValue": "0x10002",
1186 "UMask": "0x1"
1190 "Counter": "0,1,2,3",
1191 "CounterHTOff": "0,1,2,3",
1192 "EventCode": "0xB7, 0xBB",
1194 "MSRIndex": "0x1a6,0x1a7",
1195 "MSRValue": "0x3F803C0002",
1198 "UMask": "0x1"
1202 "Counter": "0,1,2,3",
1203 "CounterHTOff": "0,1,2,3",
1204 "EventCode": "0xB7, 0xBB",
1206 "MSRIndex": "0x1a6,0x1a7",
1207 "MSRValue": "0x10003C0002",
1210 "UMask": "0x1"
1214 "Counter": "0,1,2,3",
1215 "CounterHTOff": "0,1,2,3",
1216 "EventCode": "0xB7, 0xBB",
1218 "MSRIndex": "0x1a6,0x1a7",
1219 "MSRValue": "0x4003C0002",
1222 "UMask": "0x1"
1225 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1226 "Counter": "0,1,2,3",
1227 "CounterHTOff": "0,1,2,3",
1228 "EventCode": "0xB7, 0xBB",
1230 "MSRIndex": "0x1a6,0x1a7",
1231 "MSRValue": "0x1003C0002",
1234 "UMask": "0x1"
1238 "Counter": "0,1,2,3",
1239 "CounterHTOff": "0,1,2,3",
1240 "EventCode": "0xB7, 0xBB",
1242 "MSRIndex": "0x1a6,0x1a7",
1243 "MSRValue": "0x8003C0002",
1246 "UMask": "0x1"
1250 "Counter": "0,1,2,3",
1251 "CounterHTOff": "0,1,2,3",
1252 "EventCode": "0xB7, 0xBB",
1254 "MSRIndex": "0x1a6,0x1a7",
1255 "MSRValue": "0x10400",
1258 "UMask": "0x1"
1262 "Counter": "0,1,2,3",
1263 "CounterHTOff": "0,1,2,3",
1264 "EventCode": "0xB7, 0xBB",
1266 "MSRIndex": "0x1a6,0x1a7",
1267 "MSRValue": "0x3F803C0400",
1270 "UMask": "0x1"
1274 "Counter": "0,1,2,3",
1275 "CounterHTOff": "0,1,2,3",
1276 "EventCode": "0xB7, 0xBB",
1278 "MSRIndex": "0x1a6,0x1a7",
1279 "MSRValue": "0x10003C0400",
1282 "UMask": "0x1"
1286 "Counter": "0,1,2,3",
1287 "CounterHTOff": "0,1,2,3",
1288 "EventCode": "0xB7, 0xBB",
1290 "MSRIndex": "0x1a6,0x1a7",
1291 "MSRValue": "0x4003C0400",
1294 "UMask": "0x1"
1297 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1298 "Counter": "0,1,2,3",
1299 "CounterHTOff": "0,1,2,3",
1300 "EventCode": "0xB7, 0xBB",
1302 "MSRIndex": "0x1a6,0x1a7",
1303 "MSRValue": "0x1003C0400",
1306 "UMask": "0x1"
1310 "Counter": "0,1,2,3",
1311 "CounterHTOff": "0,1,2,3",
1312 "EventCode": "0xB7, 0xBB",
1314 "MSRIndex": "0x1a6,0x1a7",
1315 "MSRValue": "0x8003C0400",
1318 "UMask": "0x1"
1322 "Counter": "0,1,2,3",
1323 "CounterHTOff": "0,1,2,3",
1324 "EventCode": "0xB7, 0xBB",
1326 "MSRIndex": "0x1a6,0x1a7",
1327 "MSRValue": "0x10010",
1330 "UMask": "0x1"
1334 "Counter": "0,1,2,3",
1335 "CounterHTOff": "0,1,2,3",
1336 "EventCode": "0xB7, 0xBB",
1338 "MSRIndex": "0x1a6,0x1a7",
1339 "MSRValue": "0x3F803C0010",
1342 "UMask": "0x1"
1346 "Counter": "0,1,2,3",
1347 "CounterHTOff": "0,1,2,3",
1348 "EventCode": "0xB7, 0xBB",
1350 "MSRIndex": "0x1a6,0x1a7",
1351 "MSRValue": "0x10003C0010",
1354 "UMask": "0x1"
1358 "Counter": "0,1,2,3",
1359 "CounterHTOff": "0,1,2,3",
1360 "EventCode": "0xB7, 0xBB",
1362 "MSRIndex": "0x1a6,0x1a7",
1363 "MSRValue": "0x4003C0010",
1366 "UMask": "0x1"
1369 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1370 "Counter": "0,1,2,3",
1371 "CounterHTOff": "0,1,2,3",
1372 "EventCode": "0xB7, 0xBB",
1374 "MSRIndex": "0x1a6,0x1a7",
1375 "MSRValue": "0x1003C0010",
1378 "UMask": "0x1"
1382 "Counter": "0,1,2,3",
1383 "CounterHTOff": "0,1,2,3",
1384 "EventCode": "0xB7, 0xBB",
1386 "MSRIndex": "0x1a6,0x1a7",
1387 "MSRValue": "0x8003C0010",
1390 "UMask": "0x1"
1394 "Counter": "0,1,2,3",
1395 "CounterHTOff": "0,1,2,3",
1396 "EventCode": "0xB7, 0xBB",
1398 "MSRIndex": "0x1a6,0x1a7",
1399 "MSRValue": "0x10020",
1402 "UMask": "0x1"
1406 "Counter": "0,1,2,3",
1407 "CounterHTOff": "0,1,2,3",
1408 "EventCode": "0xB7, 0xBB",
1410 "MSRIndex": "0x1a6,0x1a7",
1411 "MSRValue": "0x3F803C0020",
1414 "UMask": "0x1"
1418 "Counter": "0,1,2,3",
1419 "CounterHTOff": "0,1,2,3",
1420 "EventCode": "0xB7, 0xBB",
1422 "MSRIndex": "0x1a6,0x1a7",
1423 "MSRValue": "0x10003C0020",
1426 "UMask": "0x1"
1430 "Counter": "0,1,2,3",
1431 "CounterHTOff": "0,1,2,3",
1432 "EventCode": "0xB7, 0xBB",
1434 "MSRIndex": "0x1a6,0x1a7",
1435 "MSRValue": "0x4003C0020",
1438 "UMask": "0x1"
1441 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1442 "Counter": "0,1,2,3",
1443 "CounterHTOff": "0,1,2,3",
1444 "EventCode": "0xB7, 0xBB",
1446 "MSRIndex": "0x1a6,0x1a7",
1447 "MSRValue": "0x1003C0020",
1450 "UMask": "0x1"
1454 "Counter": "0,1,2,3",
1455 "CounterHTOff": "0,1,2,3",
1456 "EventCode": "0xB7, 0xBB",
1458 "MSRIndex": "0x1a6,0x1a7",
1459 "MSRValue": "0x8003C0020",
1462 "UMask": "0x1"
1466 "Counter": "0,1,2,3",
1467 "CounterHTOff": "0,1,2,3",
1468 "EventCode": "0xB7, 0xBB",
1470 "MSRIndex": "0x1a6,0x1a7",
1471 "MSRValue": "0x10080",
1474 "UMask": "0x1"
1478 "Counter": "0,1,2,3",
1479 "CounterHTOff": "0,1,2,3",
1480 "EventCode": "0xB7, 0xBB",
1482 "MSRIndex": "0x1a6,0x1a7",
1483 "MSRValue": "0x3F803C0080",
1486 "UMask": "0x1"
1490 "Counter": "0,1,2,3",
1491 "CounterHTOff": "0,1,2,3",
1492 "EventCode": "0xB7, 0xBB",
1494 "MSRIndex": "0x1a6,0x1a7",
1495 "MSRValue": "0x10003C0080",
1498 "UMask": "0x1"
1502 "Counter": "0,1,2,3",
1503 "CounterHTOff": "0,1,2,3",
1504 "EventCode": "0xB7, 0xBB",
1506 "MSRIndex": "0x1a6,0x1a7",
1507 "MSRValue": "0x4003C0080",
1510 "UMask": "0x1"
1513 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1514 "Counter": "0,1,2,3",
1515 "CounterHTOff": "0,1,2,3",
1516 "EventCode": "0xB7, 0xBB",
1518 "MSRIndex": "0x1a6,0x1a7",
1519 "MSRValue": "0x1003C0080",
1522 "UMask": "0x1"
1526 "Counter": "0,1,2,3",
1527 "CounterHTOff": "0,1,2,3",
1528 "EventCode": "0xB7, 0xBB",
1530 "MSRIndex": "0x1a6,0x1a7",
1531 "MSRValue": "0x8003C0080",
1534 "UMask": "0x1"
1538 "Counter": "0,1,2,3",
1539 "CounterHTOff": "0,1,2,3",
1540 "EventCode": "0xB7, 0xBB",
1542 "MSRIndex": "0x1a6,0x1a7",
1543 "MSRValue": "0x10100",
1546 "UMask": "0x1"
1550 "Counter": "0,1,2,3",
1551 "CounterHTOff": "0,1,2,3",
1552 "EventCode": "0xB7, 0xBB",
1554 "MSRIndex": "0x1a6,0x1a7",
1555 "MSRValue": "0x3F803C0100",
1558 "UMask": "0x1"
1562 "Counter": "0,1,2,3",
1563 "CounterHTOff": "0,1,2,3",
1564 "EventCode": "0xB7, 0xBB",
1566 "MSRIndex": "0x1a6,0x1a7",
1567 "MSRValue": "0x10003C0100",
1570 "UMask": "0x1"
1574 "Counter": "0,1,2,3",
1575 "CounterHTOff": "0,1,2,3",
1576 "EventCode": "0xB7, 0xBB",
1578 "MSRIndex": "0x1a6,0x1a7",
1579 "MSRValue": "0x4003C0100",
1582 "UMask": "0x1"
1585 …that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set …
1586 "Counter": "0,1,2,3",
1587 "CounterHTOff": "0,1,2,3",
1588 "EventCode": "0xB7, 0xBB",
1590 "MSRIndex": "0x1a6,0x1a7",
1591 "MSRValue": "0x1003C0100",
1594 "UMask": "0x1"
1598 "Counter": "0,1,2,3",
1599 "CounterHTOff": "0,1,2,3",
1600 "EventCode": "0xB7, 0xBB",
1602 "MSRIndex": "0x1a6,0x1a7",
1603 "MSRValue": "0x8003C0100",
1606 "UMask": "0x1"
1610 "Counter": "0,1,2,3",
1611 "CounterHTOff": "0,1,2,3,4,5,6,7",
1612 "EventCode": "0xF4",
1616 "UMask": "0x10"
1620 "Counter": "0,1,2,3",
1621 "CounterHTOff": "0,1,2,3,4,5,6,7",
1622 "EventCode": "0x32",
1625 "UMask": "0x1"
1629 "Counter": "0,1,2,3",
1630 "CounterHTOff": "0,1,2,3,4,5,6,7",
1631 "EventCode": "0x32",
1634 "UMask": "0x8"
1638 "Counter": "0,1,2,3",
1639 "CounterHTOff": "0,1,2,3,4,5,6,7",
1640 "EventCode": "0x32",
1643 "UMask": "0x2"
1647 "Counter": "0,1,2,3",
1648 "CounterHTOff": "0,1,2,3,4,5,6,7",
1649 "EventCode": "0x32",
1652 "UMask": "0x4"