Lines Matching +full:3 +full:- +full:7
3 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3",
36 "Counter": "0,1,2,3",
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
48 "Counter": "0,1,2,3",
49 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3",
72 "CounterHTOff": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3",
84 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "Counter": "0,1,2,3",
108 "CounterHTOff": "0,1,2,3,4,5,6,7",
118 "Counter": "0,1,2,3",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
127 "Counter": "0,1,2,3",
128 "CounterHTOff": "0,1,2,3",
138 "Counter": "0,1,2,3",
139 "CounterHTOff": "0,1,2,3,4,5,6,7",
149 "Counter": "0,1,2,3",
150 "CounterHTOff": "0,1,2,3,4,5,6,7",
160 "Counter": "0,1,2,3",
161 "CounterHTOff": "0,1,2,3,4,5,6,7",
170 "Counter": "0,1,2,3",
171 "CounterHTOff": "0,1,2,3,4,5,6,7",
179 "Counter": "0,1,2,3",
180 "CounterHTOff": "0,1,2,3,4,5,6,7",
189 "Counter": "0,1,2,3",
190 "CounterHTOff": "0,1,2,3,4,5,6,7",
198 "Counter": "0,1,2,3",
199 "CounterHTOff": "0,1,2,3,4,5,6,7",
216 "Counter": "0,1,2,3",
217 "CounterHTOff": "0,1,2,3,4,5,6,7",
226 "Counter": "0,1,2,3",
227 "CounterHTOff": "0,1,2,3,4,5,6,7",
234 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
235 "Counter": "0,1,2,3",
236 "CounterHTOff": "0,1,2,3,4,5,6,7",
241 …Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
264 "Counter": "0,1,2,3",
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
274 "Counter": "0,1,2,3",
275 "CounterHTOff": "0,1,2,3,4,5,6,7",
282 "Counter": "0,1,2,3",
283 "CounterHTOff": "0,1,2,3,4,5,6,7",
292 "Counter": "0,1,2,3",
293 "CounterHTOff": "0,1,2,3,4,5,6,7",
302 "Counter": "0,1,2,3",
303 "CounterHTOff": "0,1,2,3,4,5,6,7",
312 "Counter": "0,1,2,3",
313 "CounterHTOff": "0,1,2,3,4,5,6,7",
322 "Counter": "0,1,2,3",
323 "CounterHTOff": "0,1,2,3,4,5,6,7",
332 "Counter": "0,1,2,3",
333 "CounterHTOff": "0,1,2,3",
342 "Counter": "0,1,2,3",
343 "CounterHTOff": "0,1,2,3,4,5,6,7",
352 "Counter": "0,1,2,3",
353 "CounterHTOff": "0,1,2,3,4,5,6,7",
362 "Counter": "0,1,2,3",
363 "CounterHTOff": "0,1,2,3,4,5,6,7",
371 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
372 "Counter": "0,1,2,3",
373 "CounterHTOff": "0,1,2,3,4,5,6,7",
375 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
376 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
382 "Counter": "0,1,2,3",
383 "CounterHTOff": "0,1,2,3,4,5,6,7",
392 "Counter": "0,1,2,3",
393 "CounterHTOff": "0,1,2,3,4,5,6,7",
401 "Counter": "0,1,2,3",
402 "CounterHTOff": "0,1,2,3,4,5,6,7",
411 "Counter": "0,1,2,3",
412 "CounterHTOff": "0,1,2,3,4,5,6,7",
415 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
421 "Counter": "0,1,2,3",
422 "CounterHTOff": "0,1,2,3,4,5,6,7",
434 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro…
439 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
440 "Counter": "0,1,2,3",
441 "CounterHTOff": "0,1,2,3,4,5,6,7",
445 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
450 "Counter": "0,1,2,3",
451 "CounterHTOff": "0,1,2,3,4,5,6,7",
473 "Counter": "0,2,3",
474 "CounterHTOff": "0,2,3",
486 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path …
487 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3,4,5,6,7",
496 "Counter": "0,1,2,3",
497 "CounterHTOff": "0,1,2,3,4,5,6,7",
507 "Counter": "0,1,2,3",
508 "CounterHTOff": "0,1,2,3,4,5,6,7",
516 "Counter": "0,1,2,3",
517 "CounterHTOff": "0,1,2,3,4,5,6,7",
526 "Counter": "0,1,2,3",
527 "CounterHTOff": "0,1,2,3,4,5,6,7",
536 "Counter": "0,1,2,3",
537 "CounterHTOff": "0,1,2,3,4,5,6,7",
546 "Counter": "0,1,2,3",
547 "CounterHTOff": "0,1,2,3,4,5,6,7",
550 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
556 "Counter": "0,1,2,3",
557 "CounterHTOff": "0,1,2,3,4,5,6,7",
561 …"PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector…
567 "Counter": "0,1,2,3",
568 "CounterHTOff": "0,1,2,3,4,5,6,7",
572 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
578 "Counter": "0,1,2,3",
579 "CounterHTOff": "0,1,2,3,4,5,6,7",
582 … "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
588 "Counter": "0,1,2,3",
589 "CounterHTOff": "0,1,2,3,4,5,6,7",
598 "BriefDescription": "Self-modifying code (SMC) detected.",
599 "Counter": "0,1,2,3",
600 "CounterHTOff": "0,1,2,3,4,5,6,7",
603 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
608 …"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Exa…
609 "Counter": "0,1,2,3",
610 "CounterHTOff": "0,1,2,3,4,5,6,7",
618 "Counter": "0,1,2,3",
619 "CounterHTOff": "0,1,2,3,4,5,6,7",
627 "BriefDescription": "Resource-related stall cycles",
628 "Counter": "0,1,2,3",
629 "CounterHTOff": "0,1,2,3,4,5,6,7",
632 "PublicDescription": "Counts resource-related stall cycles.",
638 "Counter": "0,1,2,3",
639 "CounterHTOff": "0,1,2,3,4,5,6,7",
642 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
648 "Counter": "0,1,2,3",
649 "CounterHTOff": "0,1,2,3,4,5,6,7",
658 "Counter": "0,1,2,3",
659 "CounterHTOff": "0,1,2,3,4,5,6,7",
667 "Counter": "0,1,2,3",
668 "CounterHTOff": "0,1,2,3,4,5,6,7",
671 …ing which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thre…
677 "Counter": "0,1,2,3",
678 "CounterHTOff": "0,1,2,3,4,5,6,7",
684 …eservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound iss…
690 "Counter": "0,1,2,3",
691 "CounterHTOff": "0,1,2,3,4,5,6,7",
694 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
700 "Counter": "0,1,2,3",
701 "CounterHTOff": "0,1,2,3,4,5,6,7",
704 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
710 "Counter": "0,1,2,3",
711 "CounterHTOff": "0,1,2,3,4,5,6,7",
714 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
719 "BriefDescription": "Cycles per thread when uops are executed in port 3",
720 "Counter": "0,1,2,3",
721 "CounterHTOff": "0,1,2,3,4,5,6,7",
724 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
730 "Counter": "0,1,2,3",
731 "CounterHTOff": "0,1,2,3,4,5,6,7",
734 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
740 "Counter": "0,1,2,3",
741 "CounterHTOff": "0,1,2,3,4,5,6,7",
744 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
750 "Counter": "0,1,2,3",
751 "CounterHTOff": "0,1,2,3,4,5,6,7",
754 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
759 "BriefDescription": "Cycles per thread when uops are executed in port 7",
760 "Counter": "0,1,2,3",
761 "CounterHTOff": "0,1,2,3,4,5,6,7",
764 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
770 "Counter": "0,1,2,3",
771 "CounterHTOff": "0,1,2,3,4,5,6,7",
779 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
780 "Counter": "0,1,2,3",
781 "CounterHTOff": "0,1,2,3,4,5,6,7",
789 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
790 "Counter": "0,1,2,3",
791 "CounterHTOff": "0,1,2,3,4,5,6,7",
799 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
800 "Counter": "0,1,2,3",
801 "CounterHTOff": "0,1,2,3,4,5,6,7",
802 "CounterMask": "3",
809 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
810 "Counter": "0,1,2,3",
811 "CounterHTOff": "0,1,2,3,4,5,6,7",
819 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
820 "Counter": "0,1,2,3",
821 "CounterHTOff": "0,1,2,3,4,5,6,7",
830 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
831 "Counter": "0,1,2,3",
832 "CounterHTOff": "0,1,2,3,4,5,6,7",
836 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
841 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3,4,5,6,7",
847 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
852 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
855 "CounterMask": "3",
858 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
863 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
864 "Counter": "0,1,2,3",
865 "CounterHTOff": "0,1,2,3,4,5,6,7",
869 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
875 "Counter": "0,1,2,3",
876 "CounterHTOff": "0,1,2,3,4,5,6,7",
886 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
887 "Counter": "0,1,2,3",
888 "CounterHTOff": "0,1,2,3,4,5,6,7",
891 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
897 "Counter": "0,1,2,3",
898 "CounterHTOff": "0,1,2,3,4,5,6,7",
907 "Counter": "0,1,2,3",
908 "CounterHTOff": "0,1,2,3,4,5,6,7",
916 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
917 "Counter": "0,1,2,3",
918 "CounterHTOff": "0,1,2,3,4,5,6,7",
926 "Counter": "0,1,2,3",
927 "CounterHTOff": "0,1,2,3,4,5,6,7",
937 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
938 "Counter": "0,1,2,3",
939 "CounterHTOff": "0,1,2,3,4,5,6,7",
942 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
947 "BriefDescription": "Number of macro-fused uops retired. (non precise)",
948 "Counter": "0,1,2,3",
949 "CounterHTOff": "0,1,2,3,4,5,6,7",
952 "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
958 "Counter": "0,1,2,3",
959 "CounterHTOff": "0,1,2,3,4,5,6,7",
968 "Counter": "0,1,2,3",
969 "CounterHTOff": "0,1,2,3,4,5,6,7",
980 "Counter": "0,1,2,3",
981 "CounterHTOff": "0,1,2,3,4,5,6,7",