Lines Matching +full:3 +full:a
3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …nc-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream…
34 "Counter": "0,1,2,3",
35 "CounterHTOff": "0,1,2,3",
47 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
48 "Counter": "0,1,2,3",
49 "CounterHTOff": "0,1,2,3",
55 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
62 "Counter": "0,1,2,3",
63 "CounterHTOff": "0,1,2,3",
76 "Counter": "0,1,2,3",
77 "CounterHTOff": "0,1,2,3",
89 "Counter": "0,1,2,3",
90 "CounterHTOff": "0,1,2,3",
102 "Counter": "0,1,2,3",
103 "CounterHTOff": "0,1,2,3",
109 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
115 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
116 "Counter": "0,1,2,3",
117 "CounterHTOff": "0,1,2,3",
128 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
129 "Counter": "0,1,2,3",
130 "CounterHTOff": "0,1,2,3",
136 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
142 …interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted …
143 "Counter": "0,1,2,3",
144 "CounterHTOff": "0,1,2,3",
155 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
156 "Counter": "0,1,2,3",
157 "CounterHTOff": "0,1,2,3",
168 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
169 "Counter": "0,1,2,3",
170 "CounterHTOff": "0,1,2,3",
176 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
182 …here the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted …
183 "Counter": "0,1,2,3",
184 "CounterHTOff": "0,1,2,3",
195 …nterval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not int…
196 "Counter": "0,1,2,3",
197 "CounterHTOff": "0,1,2,3",
208 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
209 "Counter": "0,1,2,3",
210 "CounterHTOff": "0,1,2,3",
216 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
222 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
223 "Counter": "0,1,2,3",
224 "CounterHTOff": "0,1,2,3",
235 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
236 "Counter": "0,1,2,3",
237 "CounterHTOff": "0,1,2,3",
248 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
249 "Counter": "0,1,2,3",
250 "CounterHTOff": "0,1,2,3",
261 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
262 "Counter": "0,1,2,3",
263 "CounterHTOff": "0,1,2,3",
269 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
276 "Counter": "0,1,2,3",
277 "CounterHTOff": "0,1,2,3",
289 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
290 "Counter": "0,1,2,3",
291 "CounterHTOff": "0,1,2,3,4,5,6,7",
294 …cription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
300 "Counter": "0,1,2,3",
301 "CounterHTOff": "0,1,2,3,4,5,6,7",
309 "Counter": "0,1,2,3",
310 "CounterHTOff": "0,1,2,3,4,5,6,7",
317 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
318 "Counter": "0,1,2,3",
319 "CounterHTOff": "0,1,2,3,4,5,6,7",
327 "Counter": "0,1,2,3",
328 "CounterHTOff": "0,1,2,3,4,5,6,7",
338 "Counter": "0,1,2,3",
339 "CounterHTOff": "0,1,2,3,4,5,6,7",
349 "Counter": "0,1,2,3",
350 "CounterHTOff": "0,1,2,3,4,5,6,7",
360 "Counter": "0,1,2,3",
361 "CounterHTOff": "0,1,2,3,4,5,6,7",
371 "Counter": "0,1,2,3",
372 "CounterHTOff": "0,1,2,3,4,5,6,7",
382 "Counter": "0,1,2,3",
383 "CounterHTOff": "0,1,2,3,4,5,6,7",
392 "Counter": "0,1,2,3",
393 "CounterHTOff": "0,1,2,3,4,5,6,7",
403 "Counter": "0,1,2,3",
404 "CounterHTOff": "0,1,2,3,4,5,6,7",
413 "Counter": "0,1,2,3",
414 "CounterHTOff": "0,1,2,3,4,5,6,7",
424 "Counter": "0,1,2,3",
425 "CounterHTOff": "0,1,2,3,4,5,6,7",
435 "Counter": "0,1,2,3",
436 "CounterHTOff": "0,1,2,3,4,5,6,7",
445 "Counter": "0,1,2,3",
446 "CounterHTOff": "0,1,2,3,4,5,6,7",
457 "Counter": "0,1,2,3",
458 "CounterHTOff": "0,1,2,3,4,5,6,7",
467 "Counter": "0,1,2,3",
468 "CounterHTOff": "0,1,2,3,4,5,6,7",
471 …urce Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a.…
477 "Counter": "0,1,2,3",
478 "CounterHTOff": "0,1,2,3,4,5,6,7",
488 "Counter": "0,1,2,3",
489 "CounterHTOff": "0,1,2,3,4,5,6,7",
498 …"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocatio…
499 "Counter": "0,1,2,3",
500 "CounterHTOff": "0,1,2,3,4,5,6,7",
501 "CounterMask": "3",
504 …ess than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.",
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3,4,5,6,7",
520 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
521 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3,4,5,6,7",
526 "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",