Lines Matching +full:1 +full:- +full:based
4 "Counter": "0,1",
7 "PEBS": "1",
8 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
13 "Counter": "0,1",
17 "PEBScounters": "0,1",
18 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
24 "Counter": "0,1",
27 "PEBS": "1",
28 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
34 "Counter": "0,1",
37 "PEBS": "1",
38 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
44 "Counter": "0,1",
47 "PEBS": "1",
48 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
54 "Counter": "0,1",
57 "PEBS": "1",
58 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
64 "Counter": "0,1",
67 "PEBS": "1",
68 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
74 "Counter": "0,1",
77 "PEBS": "1",
78 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
84 "Counter": "0,1",
87 "PEBS": "1",
88 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
94 "Counter": "0,1",
97 "PEBS": "1",
98 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
104 "Counter": "0,1",
107 "PEBS": "1",
108 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
113 "Counter": "0,1",
116 "PEBS": "1",
117 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
123 "Counter": "0,1",
126 "PEBS": "1",
127 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
133 "Counter": "0,1",
136 "PEBS": "1",
137 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
143 "Counter": "0,1",
146 "PEBS": "1",
147 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
153 "Counter": "0,1",
156 "PEBS": "1",
157 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
171 "Counter": "0,1",
179 "Counter": "0,1",
196 "Counter": "0,1",
205 "Counter": "Fixed counter 1",
207 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
213 "Counter": "0,1",
216 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
221 "Counter": "0,1",
229 "BriefDescription": "Self-Modifying Code detected",
230 "Counter": "0,1",
233 …ent counts the number of times that a program writes to a code section. Self-modifying code causes…
239 "Counter": "0,1",
242 …": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide …
248 "Counter": "0,1",
257 "Counter": "0,1",
260 …-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-en…
266 "Counter": "0,1",
274 "Counter": "0,1",
283 "Counter": "0,1",
290 …ropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion …
291 "Counter": "0,1",
294 …ropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion …
299 "BriefDescription": "Micro-ops retired",
300 "Counter": "0,1",
303 …-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-op…
308 "BriefDescription": "MSROM micro-ops retired",
309 "Counter": "0,1",
312 …"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MS…