Lines Matching +full:sub +full:- +full:sampled

36 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
219         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
243 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
250 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
286 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
291 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
297 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
303 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
309 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
379 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
599         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
605 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
610         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
617 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
642         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
648 …ons Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Cou…
717 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
743         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
749 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
754         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
760 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
847 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
860 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
873 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
885 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
905         "BriefDescription": "Self-modifying code (SMC) detected.",
911 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
945 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
962 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
968 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
978 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
988 …specualtive operations that were issued but not retired as well as the out-of-order engine recover…
1005 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1010 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1016 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1022 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1135 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1142 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1148 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1155 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1161 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1168 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1174 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1181 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1187         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1194         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1200         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1207         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1213         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1220         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1226         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1233         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1266         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1319 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …