Lines Matching +full:0 +full:- +full:7
4 "EventCode": "0xce",
7 "UMask": "0x2"
11 "EventCode": "0xce",
14 "UMask": "0x1"
19 "Counter": "0,1,2,3,4,5,6,7",
21 "EventCode": "0xb0",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
26 "UMask": "0x9"
31 "Counter": "0,1,2,3,4,5,6,7",
33 "EventCode": "0xb0",
35 "PEBScounters": "0,1,2,3,4,5,6,7",
36 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
39 "UMask": "0x9"
44 "Counter": "0,1,2,3,4,5,6,7",
46 "EventCode": "0xb0",
48 "PEBScounters": "0,1,2,3,4,5,6,7",
51 "UMask": "0x1"
56 "Counter": "0,1,2,3,4,5,6,7",
57 "EventCode": "0xb0",
59 "PEBScounters": "0,1,2,3,4,5,6,7",
62 "UMask": "0x8"
67 "Counter": "0,1,2,3,4,5,6,7",
69 "EventCode": "0xb0",
71 "PEBScounters": "0,1,2,3,4,5,6,7",
74 "UMask": "0x8"
79 "Counter": "0,1,2,3,4,5,6,7",
80 "EventCode": "0xc1",
82 "PEBScounters": "0,1,2,3,4,5,6,7",
86 "UMask": "0x1b"
91 "Counter": "0,1,2,3,4,5,6,7",
92 "EventCode": "0xc4",
95 "PEBScounters": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
103 "EventCode": "0xc4",
106 "PEBScounters": "0,1,2,3,4,5,6,7",
109 "UMask": "0x11"
114 "Counter": "0,1,2,3,4,5,6,7",
115 "EventCode": "0xc4",
118 "PEBScounters": "0,1,2,3,4,5,6,7",
121 "UMask": "0x10"
126 "Counter": "0,1,2,3,4,5,6,7",
127 "EventCode": "0xc4",
130 "PEBScounters": "0,1,2,3,4,5,6,7",
133 "UMask": "0x1"
138 "Counter": "0,1,2,3,4,5,6,7",
139 "EventCode": "0xc4",
142 "PEBScounters": "0,1,2,3,4,5,6,7",
145 "UMask": "0x40"
150 "Counter": "0,1,2,3,4,5,6,7",
151 "EventCode": "0xc4",
154 "PEBScounters": "0,1,2,3,4,5,6,7",
157 "UMask": "0x80"
162 "Counter": "0,1,2,3,4,5,6,7",
163 "EventCode": "0xc4",
166 "PEBScounters": "0,1,2,3,4,5,6,7",
169 "UMask": "0x2"
174 "Counter": "0,1,2,3,4,5,6,7",
175 "EventCode": "0xc4",
178 "PEBScounters": "0,1,2,3,4,5,6,7",
181 "UMask": "0x8"
186 "Counter": "0,1,2,3,4,5,6,7",
187 "EventCode": "0xc4",
190 "PEBScounters": "0,1,2,3,4,5,6,7",
193 "UMask": "0x20"
198 "Counter": "0,1,2,3,4,5,6,7",
199 "EventCode": "0xc5",
202 "PEBScounters": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
210 "EventCode": "0xc5",
213 "PEBScounters": "0,1,2,3,4,5,6,7",
216 "UMask": "0x11"
219 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
221 "Counter": "0,1,2,3,4,5,6,7",
222 "EventCode": "0xc5",
225 "PEBScounters": "0,1,2,3,4,5,6,7",
228 "UMask": "0x10"
233 "Counter": "0,1,2,3,4,5,6,7",
234 "EventCode": "0xc5",
237 "PEBScounters": "0,1,2,3,4,5,6,7",
240 "UMask": "0x1"
243 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
245 "Counter": "0,1,2,3,4,5,6,7",
246 "EventCode": "0xc5",
249 "PEBScounters": "0,1,2,3,4,5,6,7",
250 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
252 "UMask": "0x80"
257 "Counter": "0,1,2,3,4,5,6,7",
258 "EventCode": "0xc5",
261 "PEBScounters": "0,1,2,3,4,5,6,7",
264 "UMask": "0x2"
269 "Counter": "0,1,2,3,4,5,6,7",
270 "EventCode": "0xc5",
273 "PEBScounters": "0,1,2,3,4,5,6,7",
276 "UMask": "0x20"
281 "Counter": "0,1,2,3,4,5,6,7",
282 "EventCode": "0xc5",
285 "PEBScounters": "0,1,2,3,4,5,6,7",
286 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
288 "UMask": "0x8"
291 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
293 "Counter": "0,1,2,3,4,5,6,7",
294 "EventCode": "0xec",
296 "PEBScounters": "0,1,2,3,4,5,6,7",
297 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
300 "UMask": "0x10"
303 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
305 "Counter": "0,1,2,3,4,5,6,7",
306 "EventCode": "0xec",
308 "PEBScounters": "0,1,2,3,4,5,6,7",
309 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
312 "UMask": "0x20"
317 "Counter": "0,1,2,3,4,5,6,7",
318 "EventCode": "0xec",
320 "PEBScounters": "0,1,2,3,4,5,6,7",
324 "UMask": "0x70"
329 "Counter": "0,1,2,3,4,5,6,7",
330 "EventCode": "0xec",
332 "PEBScounters": "0,1,2,3,4,5,6,7",
336 "UMask": "0x2"
341 "Counter": "0,1,2,3,4,5,6,7",
342 "EventCode": "0x3c",
344 "PEBScounters": "0,1,2,3,4,5,6,7",
348 "UMask": "0x2"
353 "Counter": "0,1,2,3,4,5,6,7",
354 "EventCode": "0xec",
356 "PEBScounters": "0,1,2,3,4,5,6,7",
359 "UMask": "0x40"
363 "Counter": "0,1,2,3,4,5,6,7",
366 "EventCode": "0xec",
368 "PEBScounters": "0,1,2,3,4,5,6,7",
371 "UMask": "0x40"
375 "Counter": "0,1,2,3,4,5,6,7",
376 "EventCode": "0x3c",
378 "PEBScounters": "0,1,2,3,4,5,6,7",
379 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
382 "UMask": "0x8"
393 "UMask": "0x3"
398 "Counter": "0,1,2,3,4,5,6,7",
399 "EventCode": "0x3c",
401 "PEBScounters": "0,1,2,3,4,5,6,7",
405 "UMask": "0x1"
416 "UMask": "0x2"
421 "Counter": "0,1,2,3,4,5,6,7",
422 "EventCode": "0x3c",
424 "PEBScounters": "0,1,2,3,4,5,6,7",
432 "Counter": "0,1,2,3",
434 "EventCode": "0xa3",
436 "PEBScounters": "0,1,2,3",
439 "UMask": "0x8"
444 "Counter": "0,1,2,3",
446 "EventCode": "0xa3",
448 "PEBScounters": "0,1,2,3",
451 "UMask": "0x1"
456 "Counter": "0,1,2,3,4,5,6,7",
458 "EventCode": "0xa3",
460 "PEBScounters": "0,1,2,3,4,5,6,7",
463 "UMask": "0x10"
468 "Counter": "0,1,2,3",
470 "EventCode": "0xa3",
472 "PEBScounters": "0,1,2,3",
475 "UMask": "0xc"
480 "Counter": "0,1,2,3",
482 "EventCode": "0xa3",
484 "PEBScounters": "0,1,2,3",
487 "UMask": "0x5"
492 "Counter": "0,1,2,3,4,5,6,7",
494 "EventCode": "0xa3",
496 "PEBScounters": "0,1,2,3,4,5,6,7",
499 "UMask": "0x4"
504 "Counter": "0,1,2,3,4,5,6,7",
505 "EventCode": "0xa6",
507 "PEBScounters": "0,1,2,3,4,5,6,7",
511 "UMask": "0x2"
516 "Counter": "0,1,2,3,4,5,6,7",
517 "EventCode": "0xa6",
519 "PEBScounters": "0,1,2,3,4,5,6,7",
523 "UMask": "0x4"
528 "Counter": "0,1,2,3,4,5,6,7",
529 "EventCode": "0xa6",
531 "PEBScounters": "0,1,2,3,4,5,6,7",
535 "UMask": "0x8"
540 "Counter": "0,1,2,3,4,5,6,7",
541 "EventCode": "0xa6",
543 "PEBScounters": "0,1,2,3,4,5,6,7",
547 "UMask": "0x10"
552 "Counter": "0,1,2,3,4,5,6,7",
554 "EventCode": "0xa6",
556 "PEBScounters": "0,1,2,3,4,5,6,7",
559 "UMask": "0x21"
564 "Counter": "0,1,2,3,4,5,6,7",
566 "EventCode": "0xa6",
568 "PEBScounters": "0,1,2,3,4,5,6,7",
572 "UMask": "0x40"
577 "Counter": "0,1,2,3,4,5,6,7",
578 "EventCode": "0xa6",
580 "PEBScounters": "0,1,2,3,4,5,6,7",
581 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
584 "UMask": "0x80"
589 "Counter": "0,1,2,3",
590 "EventCode": "0x75",
592 "PEBScounters": "0,1,2,3",
596 "UMask": "0x1"
599 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
601 "Counter": "Fixed counter 0",
605 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
607 "UMask": "0x1"
610 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
612 "Counter": "0,1,2,3,4,5,6,7",
613 "EventCode": "0xc0",
616 "PEBScounters": "1,2,3,4,5,6,7",
617 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
623 "Counter": "0,1,2,3,4,5,6,7",
624 "EventCode": "0xc0",
626 "PEBScounters": "1,2,3,4,5,6,7",
628 "UMask": "0x10"
633 "Counter": "0,1,2,3,4,5,6,7",
634 "EventCode": "0xc0",
636 "PEBScounters": "1,2,3,4,5,6,7",
639 "UMask": "0x2"
642 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
644 "Counter": "Fixed counter 0",
648 …red (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
650 "UMask": "0x1"
655 "Counter": "0,1,2,3,4,5,6,7",
656 "EventCode": "0xc0",
658 "PEBScounters": "1,2,3,4,5,6,7",
660 "UMask": "0x8"
665 "Counter": "0,1,2,3,4,5,6,7",
666 "EventCode": "0xad",
668 "PEBScounters": "0,1,2,3,4,5,6,7",
672 "UMask": "0x80"
676 "Counter": "0,1,2,3,4,5,6,7",
677 "EventCode": "0xad",
679 "PEBScounters": "0,1,2,3,4,5,6,7",
682 "UMask": "0x20"
687 "Counter": "0,1,2,3,4,5,6,7",
688 "EventCode": "0xad",
690 "PEBScounters": "0,1,2,3,4,5,6,7",
694 "UMask": "0x1"
699 "Counter": "0,1,2,3,4,5,6,7",
700 "EventCode": "0xad",
702 "MSRIndex": "0x3F7",
703 "MSRValue": "0x7",
704 "PEBScounters": "0,1,2,3,4,5,6,7",
708 "UMask": "0x40"
713 "Counter": "0,1,2,3,4,5,6,7",
714 "EventCode": "0xad",
716 "PEBScounters": "0,1,2,3,4,5,6,7",
717 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
720 "UMask": "0x10"
725 "Counter": "0,1,2,3,4,5,6,7",
726 "EventCode": "0xe7",
728 "PEBScounters": "0,1,2,3,4,5,6,7",
730 "UMask": "0x13"
735 "Counter": "0,1,2,3,4,5,6,7",
736 "EventCode": "0xe7",
738 "PEBScounters": "0,1,2,3,4,5,6,7",
740 "UMask": "0xac"
743 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
745 "Counter": "0,1,2,3,4,5,6,7",
746 "EventCode": "0xe7",
748 "PEBScounters": "0,1,2,3,4,5,6,7",
749 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
751 "UMask": "0x3"
754 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
756 "Counter": "0,1,2,3,4,5,6,7",
757 "EventCode": "0xe7",
759 "PEBScounters": "0,1,2,3,4,5,6,7",
760 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
762 "UMask": "0xc"
767 "Counter": "0,1,2,3,4,5,6,7",
768 "EventCode": "0xe7",
770 "PEBScounters": "0,1,2,3,4,5,6,7",
772 "UMask": "0x80"
777 "Counter": "0,1,2,3,4,5,6,7",
778 "EventCode": "0xe7",
780 "PEBScounters": "0,1,2,3,4,5,6,7",
782 "UMask": "0x40"
787 "Counter": "0,1,2,3,4,5,6,7",
788 "EventCode": "0xe7",
790 "PEBScounters": "0,1,2,3,4,5,6,7",
792 "UMask": "0x10"
797 "Counter": "0,1,2,3,4,5,6,7",
798 "EventCode": "0xe7",
800 "PEBScounters": "0,1,2,3,4,5,6,7",
802 "UMask": "0x20"
807 "Counter": "0,1,2,3",
808 "EventCode": "0x03",
810 "PEBScounters": "0,1,2,3",
814 "UMask": "0x4"
819 "Counter": "0,1,2,3",
820 "EventCode": "0x03",
822 "PEBScounters": "0,1,2,3",
826 "UMask": "0x88"
831 "Counter": "0,1,2,3",
832 "EventCode": "0x03",
834 "PEBScounters": "0,1,2,3",
838 "UMask": "0x82"
843 "Counter": "0,1,2,3",
844 "EventCode": "0x4c",
846 "PEBScounters": "0,1,2,3",
847 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
850 "UMask": "0x1"
855 "Counter": "0,1,2,3,4,5,6,7",
857 "EventCode": "0xa8",
859 "PEBScounters": "0,1,2,3,4,5,6,7",
860 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
863 "UMask": "0x1"
868 "Counter": "0,1,2,3,4,5,6,7",
870 "EventCode": "0xa8",
872 "PEBScounters": "0,1,2,3,4,5,6,7",
873 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
876 "UMask": "0x1"
881 "Counter": "0,1,2,3,4,5,6,7",
882 "EventCode": "0xa8",
884 "PEBScounters": "0,1,2,3,4,5,6,7",
885 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
888 "UMask": "0x1"
893 "Counter": "0,1,2,3,4,5,6,7",
896 "EventCode": "0xc3",
898 "PEBScounters": "0,1,2,3,4,5,6,7",
902 "UMask": "0x1"
905 "BriefDescription": "Self-modifying code (SMC) detected.",
907 "Counter": "0,1,2,3,4,5,6,7",
908 "EventCode": "0xc3",
910 "PEBScounters": "0,1,2,3,4,5,6,7",
911 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
914 "UMask": "0x4"
919 "Counter": "0,1,2,3,4,5,6,7",
920 "EventCode": "0xe0",
922 "PEBScounters": "0,1,2,3,4,5,6,7",
925 "UMask": "0x20"
930 "Counter": "0,1,2,3,4,5,6,7",
931 "EventCode": "0xcc",
933 "PEBScounters": "0,1,2,3,4,5,6,7",
936 "UMask": "0x20"
941 "Counter": "0,1,2,3,4,5,6,7",
942 "EventCode": "0xa2",
944 "PEBScounters": "0,1,2,3,4,5,6,7",
945 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
948 "UMask": "0x8"
953 "Counter": "0,1,2,3,4,5,6,7",
954 "EventCode": "0xa2",
956 "PEBScounters": "0,1,2,3,4,5,6,7",
959 "UMask": "0x2"
962 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
964 "Counter": "0,1,2,3,4,5,6,7",
965 "EventCode": "0xa4",
967 "PEBScounters": "0,1,2,3,4,5,6,7",
968 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
971 "UMask": "0x2"
976 "EventCode": "0xa4",
978 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
981 "UMask": "0x4"
986 "EventCode": "0xa4",
988 …specualtive operations that were issued but not retired as well as the out-of-order engine recover…
991 "UMask": "0x8"
996 "Counter": "0,1,2,3,4,5,6,7",
997 "EventCode": "0xa4",
999 "PEBScounters": "0,1,2,3,4,5,6,7",
1002 "UMask": "0x10"
1005 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1010 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1013 "UMask": "0x4"
1016 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1018 "Counter": "0,1,2,3,4,5,6,7",
1019 "EventCode": "0xa4",
1021 "PEBScounters": "0,1,2,3,4,5,6,7",
1022 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1025 "UMask": "0x1"
1030 "Counter": "0,1,2,3",
1031 "EventCode": "0x76",
1033 "PEBScounters": "0,1,2,3",
1036 "UMask": "0x1"
1039 "BriefDescription": "Uops executed on port 0",
1041 "Counter": "0,1,2,3,4,5,6,7",
1042 "EventCode": "0xb2",
1044 "PEBScounters": "0,1,2,3,4,5,6,7",
1045 "PublicDescription": "Number of uops dispatch to execution port 0.",
1048 "UMask": "0x1"
1053 "Counter": "0,1,2,3,4,5,6,7",
1054 "EventCode": "0xb2",
1056 "PEBScounters": "0,1,2,3,4,5,6,7",
1060 "UMask": "0x2"
1065 "Counter": "0,1,2,3,4,5,6,7",
1066 "EventCode": "0xb2",
1068 "PEBScounters": "0,1,2,3,4,5,6,7",
1072 "UMask": "0x4"
1077 "Counter": "0,1,2,3,4,5,6,7",
1078 "EventCode": "0xb2",
1080 "PEBScounters": "0,1,2,3,4,5,6,7",
1084 "UMask": "0x10"
1089 "Counter": "0,1,2,3,4,5,6,7",
1090 "EventCode": "0xb2",
1092 "PEBScounters": "0,1,2,3,4,5,6,7",
1096 "UMask": "0x20"
1101 "Counter": "0,1,2,3,4,5,6,7",
1102 "EventCode": "0xb2",
1104 "PEBScounters": "0,1,2,3,4,5,6,7",
1108 "UMask": "0x40"
1111 "BriefDescription": "Uops executed on ports 7 and 8",
1113 "Counter": "0,1,2,3,4,5,6,7",
1114 "EventCode": "0xb2",
1116 "PEBScounters": "0,1,2,3,4,5,6,7",
1117 "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
1120 "UMask": "0x80"
1125 "Counter": "0,1,2,3,4,5,6,7",
1126 "EventCode": "0xb1",
1128 "PEBScounters": "0,1,2,3,4,5,6,7",
1132 "UMask": "0x2"
1135 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1137 "Counter": "0,1,2,3,4,5,6,7",
1139 "EventCode": "0xb1",
1141 "PEBScounters": "0,1,2,3,4,5,6,7",
1142 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1145 "UMask": "0x2"
1148 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1150 "Counter": "0,1,2,3,4,5,6,7",
1152 "EventCode": "0xb1",
1154 "PEBScounters": "0,1,2,3,4,5,6,7",
1155 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1158 "UMask": "0x2"
1161 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1163 "Counter": "0,1,2,3,4,5,6,7",
1165 "EventCode": "0xb1",
1167 "PEBScounters": "0,1,2,3,4,5,6,7",
1168 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1171 "UMask": "0x2"
1174 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1176 "Counter": "0,1,2,3,4,5,6,7",
1178 "EventCode": "0xb1",
1180 "PEBScounters": "0,1,2,3,4,5,6,7",
1181 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1184 "UMask": "0x2"
1187 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1189 "Counter": "0,1,2,3,4,5,6,7",
1191 "EventCode": "0xb1",
1193 "PEBScounters": "0,1,2,3,4,5,6,7",
1194 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1197 "UMask": "0x1"
1200 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1202 "Counter": "0,1,2,3,4,5,6,7",
1204 "EventCode": "0xb1",
1206 "PEBScounters": "0,1,2,3,4,5,6,7",
1207 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1210 "UMask": "0x1"
1213 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1215 "Counter": "0,1,2,3,4,5,6,7",
1217 "EventCode": "0xb1",
1219 "PEBScounters": "0,1,2,3,4,5,6,7",
1220 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1223 "UMask": "0x1"
1226 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1228 "Counter": "0,1,2,3,4,5,6,7",
1230 "EventCode": "0xb1",
1232 "PEBScounters": "0,1,2,3,4,5,6,7",
1233 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1236 "UMask": "0x1"
1241 "Counter": "0,1,2,3,4,5,6,7",
1243 "EventCode": "0xb1",
1246 "PEBScounters": "0,1,2,3,4,5,6,7",
1250 "UMask": "0x1"
1255 "Counter": "0,1,2,3,4,5,6,7",
1257 "EventCode": "0xb1",
1260 "PEBScounters": "0,1,2,3,4,5,6,7",
1263 "UMask": "0x1"
1266 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1268 "Counter": "0,1,2,3,4,5,6,7",
1269 "EventCode": "0xb1",
1271 "PEBScounters": "0,1,2,3,4,5,6,7",
1274 "UMask": "0x1"
1279 "Counter": "0,1,2,3,4,5,6,7",
1280 "EventCode": "0xb1",
1282 "PEBScounters": "0,1,2,3,4,5,6,7",
1286 "UMask": "0x10"
1291 "Counter": "0,1,2,3,4,5,6,7",
1292 "EventCode": "0xae",
1294 "PEBScounters": "0,1,2,3,4,5,6,7",
1298 "UMask": "0x1"
1303 "Counter": "0,1,2,3,4,5,6,7",
1305 "EventCode": "0xc2",
1307 "PEBScounters": "0,1,2,3,4,5,6,7",
1310 "UMask": "0x2"
1315 "Counter": "0,1,2,3,4,5,6,7",
1316 "EventCode": "0xc2",
1318 "PEBScounters": "0,1,2,3,4,5,6,7",
1319 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1321 "UMask": "0x1"
1326 "Counter": "0,1,2,3,4,5,6,7",
1327 "EventCode": "0xc2",
1329 "MSRIndex": "0x3F7",
1330 "MSRValue": "0x8",
1331 "PEBScounters": "0,1,2,3,4,5,6,7",
1334 "UMask": "0x4"
1339 "Counter": "0,1,2,3,4,5,6,7",
1340 "EventCode": "0xc2",
1342 "PEBScounters": "0,1,2,3,4,5,6,7",
1345 "UMask": "0x2"
1350 "Counter": "0,1,2,3,4,5,6,7",
1352 "EventCode": "0xc2",
1355 "PEBScounters": "0,1,2,3,4,5,6,7",
1358 "UMask": "0x2"
1363 "Counter": "0,1,2,3,4,5,6,7",
1365 "EventCode": "0xc2",
1368 "PEBScounters": "0,1,2,3,4,5,6,7",
1370 "UMask": "0x2"