Lines Matching +full:0 +full:- +full:3
3 …ressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specifi…
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
6 "EventCode": "0xB6",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 "EventCode": "0x14",
21 "UMask": "0x1"
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
27 "EventCode": "0x14",
30 "UMask": "0x1"
34 "Counter": "0,1,2,3",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "EventCode": "0x88",
39 "UMask": "0xff"
42 "BriefDescription": "Speculative and retired macro-conditional branches.",
43 "Counter": "0,1,2,3",
44 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "EventCode": "0x88",
48 "UMask": "0xc1"
51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
52 "Counter": "0,1,2,3",
53 "CounterHTOff": "0,1,2,3,4,5,6,7",
54 "EventCode": "0x88",
57 "UMask": "0xc2"
61 "Counter": "0,1,2,3",
62 "CounterHTOff": "0,1,2,3,4,5,6,7",
63 "EventCode": "0x88",
66 "UMask": "0xd0"
70 "Counter": "0,1,2,3",
71 "CounterHTOff": "0,1,2,3,4,5,6,7",
72 "EventCode": "0x88",
75 "UMask": "0xc4"
79 "Counter": "0,1,2,3",
80 "CounterHTOff": "0,1,2,3,4,5,6,7",
81 "EventCode": "0x88",
84 "UMask": "0xc8"
87 "BriefDescription": "Not taken macro-conditional branches.",
88 "Counter": "0,1,2,3",
89 "CounterHTOff": "0,1,2,3,4,5,6,7",
90 "EventCode": "0x88",
93 "UMask": "0x41"
96 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
97 "Counter": "0,1,2,3",
98 "CounterHTOff": "0,1,2,3,4,5,6,7",
99 "EventCode": "0x88",
102 "UMask": "0x81"
105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
106 "Counter": "0,1,2,3",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
108 "EventCode": "0x88",
111 "UMask": "0x82"
115 "Counter": "0,1,2,3",
116 "CounterHTOff": "0,1,2,3,4,5,6,7",
117 "EventCode": "0x88",
120 "UMask": "0x90"
124 "Counter": "0,1,2,3",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
126 "EventCode": "0x88",
129 "UMask": "0x84"
133 "Counter": "0,1,2,3",
134 "CounterHTOff": "0,1,2,3,4,5,6,7",
135 "EventCode": "0x88",
138 "UMask": "0xa0"
142 "Counter": "0,1,2,3",
143 "CounterHTOff": "0,1,2,3,4,5,6,7",
144 "EventCode": "0x88",
147 "UMask": "0x88"
151 "Counter": "0,1,2,3",
152 "CounterHTOff": "0,1,2,3,4,5,6,7",
153 "EventCode": "0xC4",
158 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
159 "Counter": "0,1,2,3",
160 "CounterHTOff": "0,1,2,3",
161 "EventCode": "0xC4",
165 "UMask": "0x4"
168 "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
169 "Counter": "0,1,2,3",
170 "CounterHTOff": "0,1,2,3,4,5,6,7",
171 "EventCode": "0xC4",
175 "UMask": "0x1"
179 "Counter": "0,1,2,3",
180 "CounterHTOff": "0,1,2,3,4,5,6,7",
181 "EventCode": "0xC4",
184 "UMask": "0x40"
187 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
188 "Counter": "0,1,2,3",
189 "CounterHTOff": "0,1,2,3,4,5,6,7",
190 "EventCode": "0xC4",
194 "UMask": "0x2"
197 …t and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
198 "Counter": "0,1,2,3",
199 "CounterHTOff": "0,1,2,3,4,5,6,7",
200 "EventCode": "0xC4",
204 "UMask": "0x2"
207 "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
208 "Counter": "0,1,2,3",
209 "CounterHTOff": "0,1,2,3,4,5,6,7",
210 "EventCode": "0xC4",
214 "UMask": "0x8"
217 "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
218 "Counter": "0,1,2,3",
219 "CounterHTOff": "0,1,2,3,4,5,6,7",
220 "EventCode": "0xC4",
224 "UMask": "0x20"
228 "Counter": "0,1,2,3",
229 "CounterHTOff": "0,1,2,3,4,5,6,7",
230 "EventCode": "0xC4",
233 "UMask": "0x10"
237 "Counter": "0,1,2,3",
238 "CounterHTOff": "0,1,2,3,4,5,6,7",
239 "EventCode": "0x89",
242 "UMask": "0xff"
246 "Counter": "0,1,2,3",
247 "CounterHTOff": "0,1,2,3,4,5,6,7",
248 "EventCode": "0x89",
251 "UMask": "0xc1"
255 "Counter": "0,1,2,3",
256 "CounterHTOff": "0,1,2,3,4,5,6,7",
257 "EventCode": "0x89",
260 "UMask": "0xd0"
264 "Counter": "0,1,2,3",
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
266 "EventCode": "0x89",
269 "UMask": "0xc4"
273 "Counter": "0,1,2,3",
274 "CounterHTOff": "0,1,2,3,4,5,6,7",
275 "EventCode": "0x89",
278 "UMask": "0x41"
282 "Counter": "0,1,2,3",
283 "CounterHTOff": "0,1,2,3,4,5,6,7",
284 "EventCode": "0x89",
287 "UMask": "0x81"
291 "Counter": "0,1,2,3",
292 "CounterHTOff": "0,1,2,3,4,5,6,7",
293 "EventCode": "0x89",
296 "UMask": "0x90"
300 "Counter": "0,1,2,3",
301 "CounterHTOff": "0,1,2,3,4,5,6,7",
302 "EventCode": "0x89",
305 "UMask": "0x84"
309 "Counter": "0,1,2,3",
310 "CounterHTOff": "0,1,2,3,4,5,6,7",
311 "EventCode": "0x89",
314 "UMask": "0xa0"
318 "Counter": "0,1,2,3",
319 "CounterHTOff": "0,1,2,3,4,5,6,7",
320 "EventCode": "0x89",
323 "UMask": "0x88"
327 "Counter": "0,1,2,3",
328 "CounterHTOff": "0,1,2,3,4,5,6,7",
329 "EventCode": "0xC5",
334 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
335 "Counter": "0,1,2,3",
336 "CounterHTOff": "0,1,2,3",
337 "EventCode": "0xC5",
340 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
342 "UMask": "0x4"
345 …"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).…
346 "Counter": "0,1,2,3",
347 "CounterHTOff": "0,1,2,3,4,5,6,7",
348 "EventCode": "0xC5",
352 "UMask": "0x1"
355 …ption": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
356 "Counter": "0,1,2,3",
357 "CounterHTOff": "0,1,2,3,4,5,6,7",
358 "EventCode": "0xC5",
362 "UMask": "0x2"
365 … "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
366 "Counter": "0,1,2,3",
367 "CounterHTOff": "0,1,2,3,4,5,6,7",
368 "EventCode": "0xC5",
372 "UMask": "0x10"
375 … "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
376 "Counter": "0,1,2,3",
377 "CounterHTOff": "0,1,2,3,4,5,6,7",
378 "EventCode": "0xC5",
382 "UMask": "0x20"
386 "Counter": "0,1,2,3",
387 "CounterHTOff": "0,1,2,3",
388 "EventCode": "0x3C",
391 "UMask": "0x2"
395 "Counter": "0,1,2,3",
396 "CounterHTOff": "0,1,2,3,4,5,6,7",
397 "EventCode": "0x3C",
400 "UMask": "0x1"
405 "Counter": "0,1,2,3",
406 "CounterHTOff": "0,1,2,3,4,5,6,7",
407 "EventCode": "0x3C",
410 "UMask": "0x1"
414 "Counter": "0,1,2,3",
415 "CounterHTOff": "0,1,2,3,4,5,6,7",
416 "EventCode": "0x3C",
419 "UMask": "0x2"
428 "UMask": "0x3"
432 "Counter": "0,1,2,3",
433 "CounterHTOff": "0,1,2,3,4,5,6,7",
434 "EventCode": "0x3C",
438 "UMask": "0x1"
443 "Counter": "0,1,2,3",
444 "CounterHTOff": "0,1,2,3,4,5,6,7",
445 "EventCode": "0x3C",
448 "UMask": "0x1"
457 "UMask": "0x2"
466 "UMask": "0x2"
470 "Counter": "0,1,2,3",
471 "CounterHTOff": "0,1,2,3,4,5,6,7",
472 "EventCode": "0x3C",
479 "Counter": "0,1,2,3",
480 "CounterHTOff": "0,1,2,3,4,5,6,7",
481 "EventCode": "0x3C",
486 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
490 "EventCode": "0xA3",
493 "UMask": "0x2"
496 …-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load…
497 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3,4,5,6,7",
500 "EventCode": "0xA3",
503 "UMask": "0x1"
507 "Counter": "0,1,2,3",
508 "CounterHTOff": "0,1,2,3",
510 "EventCode": "0xA3",
513 "UMask": "0x4"
516 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
520 "EventCode": "0xA3",
523 "UMask": "0x6"
526 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
527 "Counter": "0,1,2,3",
528 "CounterHTOff": "0,1,2,3",
530 "EventCode": "0xA3",
533 "UMask": "0x5"
537 "Counter": "0,1,2,3",
538 "CounterHTOff": "0,1,2,3,4,5,6,7",
539 "EventCode": "0x87",
542 "UMask": "0x4"
546 "Counter": "0,1,2,3",
547 "CounterHTOff": "0,1,2,3,4,5,6,7",
548 "EventCode": "0x87",
551 "UMask": "0x1"
555 "Counter": "Fixed counter 0",
556 "CounterHTOff": "Fixed counter 0",
558 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
560 "UMask": "0x1"
563 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
564 "Counter": "0,1,2,3",
565 "CounterHTOff": "0,1,2,3,4,5,6,7",
566 "EventCode": "0xC0",
571 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
574 "EventCode": "0xC0",
579 "UMask": "0x1"
583 "Counter": "0,1,2,3",
584 "CounterHTOff": "0,1,2,3,4,5,6,7",
585 "EventCode": "0x0D",
588 "UMask": "0x40"
592 "Counter": "0,1,2,3",
593 "CounterHTOff": "0,1,2,3,4,5,6,7",
595 "EventCode": "0x0D",
598 "UMask": "0x3"
603 "Counter": "0,1,2,3",
604 "CounterHTOff": "0,1,2,3,4,5,6,7",
606 "EventCode": "0x0D",
609 "UMask": "0x3"
613 "Counter": "0,1,2,3",
614 "CounterHTOff": "0,1,2,3,4,5,6,7",
617 "EventCode": "0x0D",
620 "UMask": "0x3"
623 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
624 "Counter": "0,1,2,3",
625 "CounterHTOff": "0,1,2,3,4,5,6,7",
626 "EventCode": "0x03",
629 "UMask": "0x10"
633 "Counter": "0,1,2,3",
634 "CounterHTOff": "0,1,2,3,4,5,6,7",
635 "EventCode": "0x03",
638 "UMask": "0x1"
642 "Counter": "0,1,2,3",
643 "CounterHTOff": "0,1,2,3,4,5,6,7",
644 "EventCode": "0x03",
647 "UMask": "0x8"
650 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
651 "Counter": "0,1,2,3",
652 "CounterHTOff": "0,1,2,3,4,5,6,7",
653 "EventCode": "0x03",
655 …re. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Opti…
657 "UMask": "0x2"
661 "Counter": "0,1,2,3",
662 "CounterHTOff": "0,1,2,3,4,5,6,7",
663 "EventCode": "0x07",
667 "UMask": "0x1"
671 "Counter": "0,1,2,3",
672 "CounterHTOff": "0,1,2,3,4,5,6,7",
673 "EventCode": "0x07",
676 "UMask": "0x8"
679 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
680 "Counter": "0,1,2,3",
681 "CounterHTOff": "0,1,2,3,4,5,6,7",
682 "EventCode": "0x4C",
685 "UMask": "0x2"
688 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
689 "Counter": "0,1,2,3",
690 "CounterHTOff": "0,1,2,3,4,5,6,7",
691 "EventCode": "0x4C",
694 "UMask": "0x1"
698 "Counter": "0,1,2,3",
699 "CounterHTOff": "0,1,2,3,4,5,6,7",
701 "EventCode": "0xA8",
704 "UMask": "0x1"
708 "Counter": "0,1,2,3",
709 "CounterHTOff": "0,1,2,3,4,5,6,7",
711 "EventCode": "0xA8",
714 "UMask": "0x1"
718 "Counter": "0,1,2,3",
719 "CounterHTOff": "0,1,2,3,4,5,6,7",
720 "EventCode": "0xA8",
723 "UMask": "0x1"
727 "Counter": "0,1,2,3",
728 "CounterHTOff": "0,1,2,3,4,5,6,7",
731 "EventCode": "0xc3",
734 "UMask": "0x1"
737 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
738 "Counter": "0,1,2,3",
739 "CounterHTOff": "0,1,2,3,4,5,6,7",
740 "EventCode": "0xC3",
742 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
744 "UMask": "0x20"
747 "BriefDescription": "Self-modifying code (SMC) detected.",
748 "Counter": "0,1,2,3",
749 "CounterHTOff": "0,1,2,3,4,5,6,7",
750 "EventCode": "0xC3",
752 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
754 "UMask": "0x4"
758 "Counter": "0,1,2,3",
759 "CounterHTOff": "0,1,2,3,4,5,6,7",
760 "EventCode": "0xC1",
763 "UMask": "0x2"
766 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
767 "Counter": "0,1,2,3",
768 "CounterHTOff": "0,1,2,3,4,5,6,7",
769 "EventCode": "0x59",
772 "UMask": "0x20"
775 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
776 "Counter": "0,1,2,3",
777 "CounterHTOff": "0,1,2,3,4,5,6,7",
779 "EventCode": "0x59",
781 …uting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mor…
783 "UMask": "0x20"
787 "Counter": "0,1,2,3",
788 "CounterHTOff": "0,1,2,3,4,5,6,7",
789 "EventCode": "0x59",
792 "UMask": "0x80"
796 "Counter": "0,1,2,3",
797 "CounterHTOff": "0,1,2,3,4,5,6,7",
798 "EventCode": "0x59",
800 …where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and …
802 "UMask": "0x40"
805 "BriefDescription": "Resource-related stall cycles.",
806 "Counter": "0,1,2,3",
807 "CounterHTOff": "0,1,2,3,4,5,6,7",
808 "EventCode": "0xA2",
811 "UMask": "0x1"
815 "Counter": "0,1,2,3",
816 "CounterHTOff": "0,1,2,3,4,5,6,7",
817 "EventCode": "0xA2",
820 "UMask": "0x2"
824 "Counter": "0,1,2,3",
825 "CounterHTOff": "0,1,2,3,4,5,6,7",
826 "EventCode": "0xA2",
829 "UMask": "0xa"
833 "Counter": "0,1,2,3",
834 "CounterHTOff": "0,1,2,3,4,5,6,7",
835 "EventCode": "0xA2",
838 "UMask": "0xe"
842 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3,4,5,6,7",
844 "EventCode": "0xA2",
847 "UMask": "0xf0"
850 "BriefDescription": "Cycles stalled due to re-order buffer full.",
851 "Counter": "0,1,2,3",
852 "CounterHTOff": "0,1,2,3,4,5,6,7",
853 "EventCode": "0xA2",
856 "UMask": "0x10"
860 "Counter": "0,1,2,3",
861 "CounterHTOff": "0,1,2,3,4,5,6,7",
862 "EventCode": "0xA2",
865 "UMask": "0x4"
869 "Counter": "0,1,2,3",
870 "CounterHTOff": "0,1,2,3,4,5,6,7",
871 "EventCode": "0xA2",
874 "UMask": "0x8"
878 "Counter": "0,1,2,3",
879 "CounterHTOff": "0,1,2,3,4,5,6,7",
880 "EventCode": "0x5B",
883 "UMask": "0xc"
887 "Counter": "0,1,2,3",
888 "CounterHTOff": "0,1,2,3,4,5,6,7",
889 "EventCode": "0x5B",
892 "UMask": "0xf"
896 "Counter": "0,1,2,3",
897 "CounterHTOff": "0,1,2,3,4,5,6,7",
898 "EventCode": "0x5B",
901 "UMask": "0x40"
905 "Counter": "0,1,2,3",
906 "CounterHTOff": "0,1,2,3,4,5,6,7",
907 "EventCode": "0x5B",
910 "UMask": "0x4f"
914 "Counter": "0,1,2,3",
915 "CounterHTOff": "0,1,2,3,4,5,6,7",
916 "EventCode": "0xCC",
919 "UMask": "0x20"
923 "Counter": "0,1,2,3",
924 "CounterHTOff": "0,1,2,3,4,5,6,7",
925 "EventCode": "0x5E",
928 "UMask": "0x1"
932 "Counter": "0,1,2,3",
933 "CounterHTOff": "0,1,2,3,4,5,6,7",
936 "EventCode": "0x5E",
940 "UMask": "0x1"
944 "Counter": "0,1,2,3",
945 "CounterHTOff": "0,1,2,3,4,5,6,7",
946 "EventCode": "0xB1",
949 "UMask": "0x2"
953 "Counter": "0,1,2,3",
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
955 "EventCode": "0xB1",
958 "UMask": "0x1"
961 "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
962 "Counter": "0,1,2,3",
963 "CounterHTOff": "0,1,2,3,4,5,6,7",
964 "EventCode": "0xA1",
967 "UMask": "0x1"
971 "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
972 "Counter": "0,1,2,3",
973 "CounterHTOff": "0,1,2,3,4,5,6,7",
974 "EventCode": "0xA1",
977 "UMask": "0x1"
981 "Counter": "0,1,2,3",
982 "CounterHTOff": "0,1,2,3,4,5,6,7",
983 "EventCode": "0xA1",
986 "UMask": "0x2"
991 "Counter": "0,1,2,3",
992 "CounterHTOff": "0,1,2,3,4,5,6,7",
993 "EventCode": "0xA1",
996 "UMask": "0x2"
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3,4,5,6,7",
1002 "EventCode": "0xA1",
1005 "UMask": "0xc"
1010 "Counter": "0,1,2,3",
1011 "CounterHTOff": "0,1,2,3,4,5,6,7",
1012 "EventCode": "0xA1",
1015 "UMask": "0xc"
1018 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
1019 "Counter": "0,1,2,3",
1020 "CounterHTOff": "0,1,2,3,4,5,6,7",
1021 "EventCode": "0xA1",
1024 "UMask": "0x30"
1028 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
1029 "Counter": "0,1,2,3",
1030 "CounterHTOff": "0,1,2,3,4,5,6,7",
1031 "EventCode": "0xA1",
1034 "UMask": "0x30"
1038 "Counter": "0,1,2,3",
1039 "CounterHTOff": "0,1,2,3,4,5,6,7",
1040 "EventCode": "0xA1",
1043 "UMask": "0x40"
1048 "Counter": "0,1,2,3",
1049 "CounterHTOff": "0,1,2,3,4,5,6,7",
1050 "EventCode": "0xA1",
1053 "UMask": "0x40"
1057 "Counter": "0,1,2,3",
1058 "CounterHTOff": "0,1,2,3,4,5,6,7",
1059 "EventCode": "0xA1",
1062 "UMask": "0x80"
1067 "Counter": "0,1,2,3",
1068 "CounterHTOff": "0,1,2,3,4,5,6,7",
1069 "EventCode": "0xA1",
1072 "UMask": "0x80"
1075 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1076 "Counter": "0,1,2,3",
1077 "CounterHTOff": "0,1,2,3,4,5,6,7",
1079 "EventCode": "0xB1",
1082 "UMask": "0x2"
1085 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1086 "Counter": "0,1,2,3",
1087 "CounterHTOff": "0,1,2,3,4,5,6,7",
1089 "EventCode": "0xB1",
1092 "UMask": "0x2"
1095 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1096 "Counter": "0,1,2,3",
1097 "CounterHTOff": "0,1,2,3,4,5,6,7",
1098 "CounterMask": "3",
1099 "EventCode": "0xB1",
1102 "UMask": "0x2"
1105 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1106 "Counter": "0,1,2,3",
1107 "CounterHTOff": "0,1,2,3,4,5,6,7",
1109 "EventCode": "0xB1",
1112 "UMask": "0x2"
1115 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1116 "Counter": "0,1,2,3",
1117 "CounterHTOff": "0,1,2,3,4,5,6,7",
1118 "EventCode": "0xB1",
1122 "UMask": "0x2"
1126 "Counter": "0,1,2,3",
1127 "CounterHTOff": "0,1,2,3,4,5,6,7",
1128 "EventCode": "0x0E",
1130 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1132 "UMask": "0x1"
1137 "Counter": "0,1,2,3",
1138 "CounterHTOff": "0,1,2,3",
1140 "EventCode": "0x0E",
1144 "UMask": "0x1"
1148 "Counter": "0,1,2,3",
1149 "CounterHTOff": "0,1,2,3",
1151 "EventCode": "0x0E",
1155 "UMask": "0x1"
1158 "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
1159 "Counter": "0,1,2,3",
1160 "CounterHTOff": "0,1,2,3,4,5,6,7",
1161 "EventCode": "0xC2",
1164 "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
1166 "UMask": "0x1"
1170 "Counter": "0,1,2,3",
1171 "CounterHTOff": "0,1,2,3",
1173 "EventCode": "0xC2",
1177 "UMask": "0x1"
1180 "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
1181 "Counter": "0,1,2,3",
1182 "CounterHTOff": "0,1,2,3,4,5,6,7",
1183 "EventCode": "0xC2",
1186 …- meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determini…
1188 "UMask": "0x2"
1192 "Counter": "0,1,2,3",
1193 "CounterHTOff": "0,1,2,3",
1195 "EventCode": "0xC2",
1199 "UMask": "0x1"
1203 "Counter": "0,1,2,3",
1204 "CounterHTOff": "0,1,2,3",
1206 "EventCode": "0xC2",
1210 "UMask": "0x1"