Lines Matching +full:3 +full:- +full:line
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
12 …ription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3",
23 "CounterHTOff": "0,1,2,3,4,5,6,7",
30 "BriefDescription": "L1D data line replacements.",
31 "Counter": "0,1,2,3",
32 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 …event counts L1D data line replacements. Replacements occur when a new line is brought into the c…
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
91 "Counter": "0,1,2,3",
92 "CounterHTOff": "0,1,2,3,4,5,6,7",
100 "Counter": "0,1,2,3",
101 "CounterHTOff": "0,1,2,3,4,5,6,7",
109 "Counter": "0,1,2,3",
110 "CounterHTOff": "0,1,2,3,4,5,6,7",
118 "Counter": "0,1,2,3",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
126 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
127 "Counter": "0,1,2,3",
128 "CounterHTOff": "0,1,2,3,4,5,6,7",
136 "Counter": "0,1,2,3",
137 "CounterHTOff": "0,1,2,3,4,5,6,7",
146 "Counter": "0,1,2,3",
147 "CounterHTOff": "0,1,2,3,4,5,6,7",
155 "Counter": "0,1,2,3",
156 "CounterHTOff": "0,1,2,3,4,5,6,7",
164 "Counter": "0,1,2,3",
165 "CounterHTOff": "0,1,2,3,4,5,6,7",
173 "Counter": "0,1,2,3",
174 "CounterHTOff": "0,1,2,3,4,5,6,7",
182 "Counter": "0,1,2,3",
183 "CounterHTOff": "0,1,2,3,4,5,6,7",
191 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3",
201 "CounterHTOff": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3",
210 "CounterHTOff": "0,1,2,3,4,5,6,7",
218 "Counter": "0,1,2,3",
219 "CounterHTOff": "0,1,2,3,4,5,6,7",
227 "Counter": "0,1,2,3",
228 "CounterHTOff": "0,1,2,3,4,5,6,7",
236 "Counter": "0,1,2,3",
237 "CounterHTOff": "0,1,2,3,4,5,6,7",
245 "Counter": "0,1,2,3",
246 "CounterHTOff": "0,1,2,3,4,5,6,7",
254 "Counter": "0,1,2,3",
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
263 "Counter": "0,1,2,3",
264 "CounterHTOff": "0,1,2,3,4,5,6,7",
272 "Counter": "0,1,2,3",
273 "CounterHTOff": "0,1,2,3,4,5,6,7",
281 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7",
290 "Counter": "0,1,2,3",
291 "CounterHTOff": "0,1,2,3,4,5,6,7",
299 "Counter": "0,1,2,3",
300 "CounterHTOff": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3",
309 "CounterHTOff": "0,1,2,3,4,5,6,7",
317 "Counter": "0,1,2,3",
318 "CounterHTOff": "0,1,2,3,4,5,6,7",
326 "Counter": "0,1,2,3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7",
335 "Counter": "0,1,2,3",
336 "CounterHTOff": "0,1,2,3,4,5,6,7",
344 "Counter": "0,1,2,3",
345 "CounterHTOff": "0,1,2,3,4,5,6,7",
353 "Counter": "0,1,2,3",
354 "CounterHTOff": "0,1,2,3,4,5,6,7",
362 "Counter": "0,1,2,3",
363 "CounterHTOff": "0,1,2,3,4,5,6,7",
371 "Counter": "0,1,2,3",
372 "CounterHTOff": "0,1,2,3,4,5,6,7",
380 "Counter": "0,1,2,3",
381 "CounterHTOff": "0,1,2,3,4,5,6,7",
389 "Counter": "0,1,2,3",
390 "CounterHTOff": "0,1,2,3,4,5,6,7",
398 "Counter": "0,1,2,3",
399 "CounterHTOff": "0,1,2,3,4,5,6,7",
407 "Counter": "0,1,2,3",
408 "CounterHTOff": "0,1,2,3,4,5,6,7",
416 "Counter": "0,1,2,3",
417 "CounterHTOff": "0,1,2,3,4,5,6,7",
425 "Counter": "0,1,2,3",
426 "CounterHTOff": "0,1,2,3,4,5,6,7",
433 "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
434 "Counter": "0,1,2,3",
435 "CounterHTOff": "0,1,2,3,4,5,6,7",
442 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
443 "Counter": "0,1,2,3",
444 "CounterHTOff": "0,1,2,3,4,5,6,7",
451 …d load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise E…
452 "Counter": "0,1,2,3",
453 "CounterHTOff": "0,1,2,3",
457 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
462 …Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
463 "Counter": "0,1,2,3",
464 "CounterHTOff": "0,1,2,3",
468 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
473 …d uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise …
474 "Counter": "0,1,2,3",
475 "CounterHTOff": "0,1,2,3",
483 …ed load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
484 "Counter": "0,1,2,3",
485 "CounterHTOff": "0,1,2,3",
493 … uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
494 "Counter": "0,1,2,3",
495 "CounterHTOff": "0,1,2,3",
499 …-level (L3) cache. This means that the load is usually satisfied from memory in a client system or…
504 … L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - …
505 "Counter": "0,1,2,3",
506 "CounterHTOff": "0,1,2,3",
514 …"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).…
515 "Counter": "0,1,2,3",
516 "CounterHTOff": "0,1,2,3",
524 …"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).…
525 "Counter": "0,1,2,3",
526 "CounterHTOff": "0,1,2,3",
534 …ad uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).",
535 "Counter": "0,1,2,3",
536 "CounterHTOff": "0,1,2,3",
540 …t counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise…
545 "BriefDescription": "All retired load uops. (Precise Event - PEBS).",
546 "Counter": "0,1,2,3",
547 "CounterHTOff": "0,1,2,3",
556 "BriefDescription": "All retired store uops. (Precise Event - PEBS).",
557 "Counter": "0,1,2,3",
558 "CounterHTOff": "0,1,2,3",
562 … "PublicDescription": "This event counts the number of store uops retired. (Precise Event - PEBS)",
567 "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).",
568 "Counter": "0,1,2,3",
569 "CounterHTOff": "0,1,2,3",
577 …fDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).",
578 "Counter": "0,1,2,3",
579 "CounterHTOff": "0,1,2,3",
583 …nts line-splitted load uops retired to the architected path. A line split is across 64B cache-line…
588 …Description": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).",
589 "Counter": "0,1,2,3",
590 "CounterHTOff": "0,1,2,3",
594 …ts line-splitted store uops retired to the architected path. A line split is across 64B cache-line…
599 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).",
600 "Counter": "0,1,2,3",
601 "CounterHTOff": "0,1,2,3",
609 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).",
610 "Counter": "0,1,2,3",
611 "CounterHTOff": "0,1,2,3",
620 "Counter": "0,1,2,3",
621 "CounterHTOff": "0,1,2,3,4,5,6,7",
629 "Counter": "0,1,2,3",
630 "CounterHTOff": "0,1,2,3,4,5,6,7",
638 "Counter": "0,1,2,3",
639 "CounterHTOff": "0,1,2,3,4,5,6,7",
647 "Counter": "0,1,2,3",
648 "CounterHTOff": "0,1,2,3,4,5,6,7",
656 "Counter": "0,1,2,3",
657 "CounterHTOff": "0,1,2,3,4,5,6,7",
665 "Counter": "0,1,2,3",
666 "CounterHTOff": "0,1,2,3,4,5,6,7",
674 "Counter": "0,1,2,3",
675 "CounterHTOff": "0,1,2,3,4,5,6,7",
684 "Counter": "0,1,2,3",
685 "CounterHTOff": "0,1,2,3,4,5,6,7",
694 "Counter": "0,1,2,3",
695 "CounterHTOff": "0,1,2,3,4,5,6,7",
704 "Counter": "0,1,2,3",
705 "CounterHTOff": "0,1,2,3,4,5,6,7",
713 "Counter": "0,1,2,3",
714 "CounterHTOff": "0,1,2,3,4,5,6,7",
723 "Counter": "0,1,2,3",
724 "CounterHTOff": "0,1,2,3,4,5,6,7",
731 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
732 "Counter": "0,1,2,3",
733 "CounterHTOff": "0,1,2,3",
743 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
744 "Counter": "0,1,2,3",
745 "CounterHTOff": "0,1,2,3",
756 "Counter": "0,1,2,3",
757 "CounterHTOff": "0,1,2,3",
768 "Counter": "0,1,2,3",
769 "CounterHTOff": "0,1,2,3",
780 "Counter": "0,1,2,3",
781 "CounterHTOff": "0,1,2,3",
791 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
792 "Counter": "0,1,2,3",
793 "CounterHTOff": "0,1,2,3",
803 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
804 "Counter": "0,1,2,3",
805 "CounterHTOff": "0,1,2,3",
815 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
816 "Counter": "0,1,2,3",
817 "CounterHTOff": "0,1,2,3",
828 "Counter": "0,1,2,3",
829 "CounterHTOff": "0,1,2,3",
840 "Counter": "0,1,2,3",
841 "CounterHTOff": "0,1,2,3",
851 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
852 "Counter": "0,1,2,3",
853 "CounterHTOff": "0,1,2,3",
863 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
864 "Counter": "0,1,2,3",
865 "CounterHTOff": "0,1,2,3",
875 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
876 "Counter": "0,1,2,3",
877 "CounterHTOff": "0,1,2,3",
888 "Counter": "0,1,2,3",
889 "CounterHTOff": "0,1,2,3",
900 "Counter": "0,1,2,3",
901 "CounterHTOff": "0,1,2,3",
911 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
912 "Counter": "0,1,2,3",
913 "CounterHTOff": "0,1,2,3",
923 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
924 "Counter": "0,1,2,3",
925 "CounterHTOff": "0,1,2,3",
935 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
936 "Counter": "0,1,2,3",
937 "CounterHTOff": "0,1,2,3",
948 "Counter": "0,1,2,3",
949 "CounterHTOff": "0,1,2,3",
960 "Counter": "0,1,2,3",
961 "CounterHTOff": "0,1,2,3",
971 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
972 "Counter": "0,1,2,3",
973 "CounterHTOff": "0,1,2,3",
983 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
984 "Counter": "0,1,2,3",
985 "CounterHTOff": "0,1,2,3",
995 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
996 "Counter": "0,1,2,3",
997 "CounterHTOff": "0,1,2,3",
1008 "Counter": "0,1,2,3",
1009 "CounterHTOff": "0,1,2,3",
1020 "Counter": "0,1,2,3",
1021 "CounterHTOff": "0,1,2,3",
1032 "Counter": "0,1,2,3",
1033 "CounterHTOff": "0,1,2,3",
1043 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1044 "Counter": "0,1,2,3",
1045 "CounterHTOff": "0,1,2,3",
1055 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1056 "Counter": "0,1,2,3",
1057 "CounterHTOff": "0,1,2,3",
1067 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1068 "Counter": "0,1,2,3",
1069 "CounterHTOff": "0,1,2,3",
1080 "Counter": "0,1,2,3",
1081 "CounterHTOff": "0,1,2,3",
1092 "Counter": "0,1,2,3",
1093 "CounterHTOff": "0,1,2,3",
1104 "Counter": "0,1,2,3",
1105 "CounterHTOff": "0,1,2,3",
1115 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1116 "Counter": "0,1,2,3",
1117 "CounterHTOff": "0,1,2,3",
1127 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1128 "Counter": "0,1,2,3",
1129 "CounterHTOff": "0,1,2,3",
1139 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1140 "Counter": "0,1,2,3",
1141 "CounterHTOff": "0,1,2,3",
1152 "Counter": "0,1,2,3",
1153 "CounterHTOff": "0,1,2,3",
1164 "Counter": "0,1,2,3",
1165 "CounterHTOff": "0,1,2,3",
1176 "Counter": "0,1,2,3",
1177 "CounterHTOff": "0,1,2,3",
1188 "Counter": "0,1,2,3",
1189 "CounterHTOff": "0,1,2,3",
1200 "Counter": "0,1,2,3",
1201 "CounterHTOff": "0,1,2,3",
1211 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1212 "Counter": "0,1,2,3",
1213 "CounterHTOff": "0,1,2,3",
1223 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1224 "Counter": "0,1,2,3",
1225 "CounterHTOff": "0,1,2,3",
1235 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1236 "Counter": "0,1,2,3",
1237 "CounterHTOff": "0,1,2,3",
1248 "Counter": "0,1,2,3",
1249 "CounterHTOff": "0,1,2,3",
1260 "Counter": "0,1,2,3",
1261 "CounterHTOff": "0,1,2,3",
1272 "Counter": "0,1,2,3",
1273 "CounterHTOff": "0,1,2,3",
1283 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1284 "Counter": "0,1,2,3",
1285 "CounterHTOff": "0,1,2,3",
1295 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1296 "Counter": "0,1,2,3",
1297 "CounterHTOff": "0,1,2,3",
1307 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1308 "Counter": "0,1,2,3",
1309 "CounterHTOff": "0,1,2,3",
1320 "Counter": "0,1,2,3",
1321 "CounterHTOff": "0,1,2,3",
1332 "Counter": "0,1,2,3",
1333 "CounterHTOff": "0,1,2,3",
1344 "Counter": "0,1,2,3",
1345 "CounterHTOff": "0,1,2,3",
1355 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1356 "Counter": "0,1,2,3",
1357 "CounterHTOff": "0,1,2,3",
1367 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1368 "Counter": "0,1,2,3",
1369 "CounterHTOff": "0,1,2,3",
1379 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1380 "Counter": "0,1,2,3",
1381 "CounterHTOff": "0,1,2,3",
1392 "Counter": "0,1,2,3",
1393 "CounterHTOff": "0,1,2,3",
1404 "Counter": "0,1,2,3",
1405 "CounterHTOff": "0,1,2,3",
1415 …acheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted …
1416 "Counter": "0,1,2,3",
1417 "CounterHTOff": "0,1,2,3",
1427 …"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core…
1428 "Counter": "0,1,2,3",
1429 "CounterHTOff": "0,1,2,3",
1440 "Counter": "0,1,2,3",
1441 "CounterHTOff": "0,1,2,3",
1452 "Counter": "0,1,2,3",
1453 "CounterHTOff": "0,1,2,3",
1464 "Counter": "0,1,2,3",
1465 "CounterHTOff": "0,1,2,3",
1475 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1476 "Counter": "0,1,2,3",
1477 "CounterHTOff": "0,1,2,3",
1487 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1488 "Counter": "0,1,2,3",
1489 "CounterHTOff": "0,1,2,3",
1499 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1500 "Counter": "0,1,2,3",
1501 "CounterHTOff": "0,1,2,3",
1512 "Counter": "0,1,2,3",
1513 "CounterHTOff": "0,1,2,3",
1524 "Counter": "0,1,2,3",
1525 "CounterHTOff": "0,1,2,3",
1535 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1536 "Counter": "0,1,2,3",
1537 "CounterHTOff": "0,1,2,3",
1547 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1548 "Counter": "0,1,2,3",
1549 "CounterHTOff": "0,1,2,3",
1559 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1560 "Counter": "0,1,2,3",
1561 "CounterHTOff": "0,1,2,3",
1572 "Counter": "0,1,2,3",
1573 "CounterHTOff": "0,1,2,3",
1584 "Counter": "0,1,2,3",
1585 "CounterHTOff": "0,1,2,3",
1595 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1596 "Counter": "0,1,2,3",
1597 "CounterHTOff": "0,1,2,3",
1607 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1608 "Counter": "0,1,2,3",
1609 "CounterHTOff": "0,1,2,3",
1619 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1620 "Counter": "0,1,2,3",
1621 "CounterHTOff": "0,1,2,3",
1632 "Counter": "0,1,2,3",
1633 "CounterHTOff": "0,1,2,3",
1644 "Counter": "0,1,2,3",
1645 "CounterHTOff": "0,1,2,3",
1655 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1656 "Counter": "0,1,2,3",
1657 "CounterHTOff": "0,1,2,3",
1667 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1668 "Counter": "0,1,2,3",
1669 "CounterHTOff": "0,1,2,3",
1679 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1680 "Counter": "0,1,2,3",
1681 "CounterHTOff": "0,1,2,3",
1692 "Counter": "0,1,2,3",
1693 "CounterHTOff": "0,1,2,3",
1704 "Counter": "0,1,2,3",
1705 "CounterHTOff": "0,1,2,3",
1715 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1716 "Counter": "0,1,2,3",
1717 "CounterHTOff": "0,1,2,3",
1727 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1728 "Counter": "0,1,2,3",
1729 "CounterHTOff": "0,1,2,3",
1739 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1740 "Counter": "0,1,2,3",
1741 "CounterHTOff": "0,1,2,3",
1752 "Counter": "0,1,2,3",
1753 "CounterHTOff": "0,1,2,3",
1764 "Counter": "0,1,2,3",
1765 "CounterHTOff": "0,1,2,3",
1775 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1776 "Counter": "0,1,2,3",
1777 "CounterHTOff": "0,1,2,3",
1787 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1788 "Counter": "0,1,2,3",
1789 "CounterHTOff": "0,1,2,3",
1799 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1800 "Counter": "0,1,2,3",
1801 "CounterHTOff": "0,1,2,3",
1812 "Counter": "0,1,2,3",
1813 "CounterHTOff": "0,1,2,3",
1824 "Counter": "0,1,2,3",
1825 "CounterHTOff": "0,1,2,3",
1836 "Counter": "0,1,2,3",
1837 "CounterHTOff": "0,1,2,3",
1847 …ts requests where the address of an atomic lock instruction spans a cache line boundary or the loc…
1848 "Counter": "0,1,2,3",
1849 "CounterHTOff": "0,1,2,3",
1859 "BriefDescription": "Counts non-temporal stores.",
1860 "Counter": "0,1,2,3",
1861 "CounterHTOff": "0,1,2,3",
1872 "Counter": "0,1,2,3",
1873 "CounterHTOff": "0,1,2,3,4,5,6,7",