Lines Matching +full:3 +full:- +full:7
3 …ressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specifi…
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "BriefDescription": "Speculative and retired macro-conditional branches.",
43 "Counter": "0,1,2,3",
44 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
52 "Counter": "0,1,2,3",
53 "CounterHTOff": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3",
62 "CounterHTOff": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3",
71 "CounterHTOff": "0,1,2,3,4,5,6,7",
79 "Counter": "0,1,2,3",
80 "CounterHTOff": "0,1,2,3,4,5,6,7",
87 "BriefDescription": "Not taken macro-conditional branches.",
88 "Counter": "0,1,2,3",
89 "CounterHTOff": "0,1,2,3,4,5,6,7",
96 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
97 "Counter": "0,1,2,3",
98 "CounterHTOff": "0,1,2,3,4,5,6,7",
105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
106 "Counter": "0,1,2,3",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "Counter": "0,1,2,3",
116 "CounterHTOff": "0,1,2,3,4,5,6,7",
124 "Counter": "0,1,2,3",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
133 "Counter": "0,1,2,3",
134 "CounterHTOff": "0,1,2,3,4,5,6,7",
142 "Counter": "0,1,2,3",
143 "CounterHTOff": "0,1,2,3,4,5,6,7",
151 "Counter": "0,1,2,3",
152 "CounterHTOff": "0,1,2,3,4,5,6,7",
158 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
159 "Counter": "0,1,2,3",
160 "CounterHTOff": "0,1,2,3",
169 "Counter": "0,1,2,3",
170 "CounterHTOff": "0,1,2,3,4,5,6,7",
179 "Counter": "0,1,2,3",
180 "CounterHTOff": "0,1,2,3,4,5,6,7",
188 "Counter": "0,1,2,3",
189 "CounterHTOff": "0,1,2,3,4,5,6,7",
198 "Counter": "0,1,2,3",
199 "CounterHTOff": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3",
209 "CounterHTOff": "0,1,2,3,4,5,6,7",
218 "Counter": "0,1,2,3",
219 "CounterHTOff": "0,1,2,3,4,5,6,7",
227 "Counter": "0,1,2,3",
228 "CounterHTOff": "0,1,2,3,4,5,6,7",
236 "Counter": "0,1,2,3",
237 "CounterHTOff": "0,1,2,3,4,5,6,7",
245 "Counter": "0,1,2,3",
246 "CounterHTOff": "0,1,2,3,4,5,6,7",
254 "Counter": "0,1,2,3",
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
263 "Counter": "0,1,2,3",
264 "CounterHTOff": "0,1,2,3,4,5,6,7",
272 "Counter": "0,1,2,3",
273 "CounterHTOff": "0,1,2,3,4,5,6,7",
281 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7",
290 "Counter": "0,1,2,3",
291 "CounterHTOff": "0,1,2,3,4,5,6,7",
299 "Counter": "0,1,2,3",
300 "CounterHTOff": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3",
309 "CounterHTOff": "0,1,2,3,4,5,6,7",
317 "Counter": "0,1,2,3",
318 "CounterHTOff": "0,1,2,3,4,5,6,7",
324 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
325 "Counter": "0,1,2,3",
326 "CounterHTOff": "0,1,2,3",
330 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
336 "Counter": "0,1,2,3",
337 "CounterHTOff": "0,1,2,3,4,5,6,7",
346 "Counter": "0,1,2,3",
347 "CounterHTOff": "0,1,2,3,4,5,6,7",
356 "Counter": "0,1,2,3",
357 "CounterHTOff": "0,1,2,3,4,5,6,7",
366 "Counter": "0,1,2,3",
367 "CounterHTOff": "0,1,2,3,4,5,6,7",
376 "Counter": "0,1,2,3",
377 "CounterHTOff": "0,1,2,3",
385 "Counter": "0,1,2,3",
386 "CounterHTOff": "0,1,2,3,4,5,6,7",
395 "Counter": "0,1,2,3",
396 "CounterHTOff": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3",
405 "CounterHTOff": "0,1,2,3,4,5,6,7",
422 "Counter": "0,1,2,3",
423 "CounterHTOff": "0,1,2,3,4,5,6,7",
433 "Counter": "0,1,2,3",
434 "CounterHTOff": "0,1,2,3,4,5,6,7",
460 "Counter": "0,1,2,3",
461 "CounterHTOff": "0,1,2,3,4,5,6,7",
469 "Counter": "0,1,2,3",
470 "CounterHTOff": "0,1,2,3,4,5,6,7",
476 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
486 …"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-com…
487 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3,4,5,6,7",
497 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3",
506 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
516 …scription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this th…
517 "Counter": "0,1,2,3",
518 "CounterHTOff": "0,1,2,3",
527 "Counter": "0,1,2,3",
528 "CounterHTOff": "0,1,2,3,4,5,6,7",
536 "Counter": "0,1,2,3",
537 "CounterHTOff": "0,1,2,3,4,5,6,7",
548 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
553 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
554 "Counter": "0,1,2,3",
555 "CounterHTOff": "0,1,2,3,4,5,6,7",
561 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
573 "Counter": "0,1,2,3",
574 "CounterHTOff": "0,1,2,3,4,5,6,7",
582 "Counter": "0,1,2,3",
583 "CounterHTOff": "0,1,2,3,4,5,6,7",
593 "Counter": "0,1,2,3",
594 "CounterHTOff": "0,1,2,3,4,5,6,7",
603 "Counter": "0,1,2,3",
604 "CounterHTOff": "0,1,2,3,4,5,6,7",
613 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
614 "Counter": "0,1,2,3",
615 "CounterHTOff": "0,1,2,3,4,5,6,7",
623 "Counter": "0,1,2,3",
624 "CounterHTOff": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3",
633 "CounterHTOff": "0,1,2,3,4,5,6,7",
640 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
641 "Counter": "0,1,2,3",
642 "CounterHTOff": "0,1,2,3,4,5,6,7",
645 …tore. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Opti…
651 "Counter": "0,1,2,3",
652 "CounterHTOff": "0,1,2,3,4,5,6,7",
661 "Counter": "0,1,2,3",
662 "CounterHTOff": "0,1,2,3,4,5,6,7",
669 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
670 "Counter": "0,1,2,3",
671 "CounterHTOff": "0,1,2,3,4,5,6,7",
678 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
679 "Counter": "0,1,2,3",
680 "CounterHTOff": "0,1,2,3,4,5,6,7",
688 "Counter": "0,1,2,3",
689 "CounterHTOff": "0,1,2,3,4,5,6,7",
698 "Counter": "0,1,2,3",
699 "CounterHTOff": "0,1,2,3,4,5,6,7",
708 "Counter": "0,1,2,3",
709 "CounterHTOff": "0,1,2,3,4,5,6,7",
717 "Counter": "0,1,2,3",
718 "CounterHTOff": "0,1,2,3,4,5,6,7",
728 "Counter": "0,1,2,3",
729 "CounterHTOff": "0,1,2,3,4,5,6,7",
732 …"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flo…
737 "BriefDescription": "Self-modifying code (SMC) detected.",
738 "Counter": "0,1,2,3",
739 "CounterHTOff": "0,1,2,3,4,5,6,7",
742 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
748 "Counter": "0,1,2,3",
749 "CounterHTOff": "0,1,2,3,4,5,6,7",
756 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
757 "Counter": "0,1,2,3",
758 "CounterHTOff": "0,1,2,3,4,5,6,7",
765 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
766 "Counter": "0,1,2,3",
767 "CounterHTOff": "0,1,2,3,4,5,6,7",
771 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
777 "Counter": "0,1,2,3",
778 "CounterHTOff": "0,1,2,3,4,5,6,7",
786 "Counter": "0,1,2,3",
787 "CounterHTOff": "0,1,2,3,4,5,6,7",
790 … where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and I…
795 "BriefDescription": "Resource-related stall cycles.",
796 "Counter": "0,1,2,3",
797 "CounterHTOff": "0,1,2,3,4,5,6,7",
805 "Counter": "0,1,2,3",
806 "CounterHTOff": "0,1,2,3,4,5,6,7",
814 "Counter": "0,1,2,3",
815 "CounterHTOff": "0,1,2,3,4,5,6,7",
823 "Counter": "0,1,2,3",
824 "CounterHTOff": "0,1,2,3,4,5,6,7",
832 "Counter": "0,1,2,3",
833 "CounterHTOff": "0,1,2,3,4,5,6,7",
840 "BriefDescription": "Cycles stalled due to re-order buffer full.",
841 "Counter": "0,1,2,3",
842 "CounterHTOff": "0,1,2,3,4,5,6,7",
850 "Counter": "0,1,2,3",
851 "CounterHTOff": "0,1,2,3,4,5,6,7",
859 "Counter": "0,1,2,3",
860 "CounterHTOff": "0,1,2,3,4,5,6,7",
868 "Counter": "0,1,2,3",
869 "CounterHTOff": "0,1,2,3,4,5,6,7",
877 "Counter": "0,1,2,3",
878 "CounterHTOff": "0,1,2,3,4,5,6,7",
886 "Counter": "0,1,2,3",
887 "CounterHTOff": "0,1,2,3,4,5,6,7",
895 "Counter": "0,1,2,3",
896 "CounterHTOff": "0,1,2,3,4,5,6,7",
904 "Counter": "0,1,2,3",
905 "CounterHTOff": "0,1,2,3,4,5,6,7",
913 "Counter": "0,1,2,3",
914 "CounterHTOff": "0,1,2,3,4,5,6,7",
922 "Counter": "0,1,2,3",
923 "CounterHTOff": "0,1,2,3,4,5,6,7",
934 "Counter": "0,1,2,3",
935 "CounterHTOff": "0,1,2,3,4,5,6,7",
943 "Counter": "0,1,2,3",
944 "CounterHTOff": "0,1,2,3,4,5,6,7",
952 "Counter": "0,1,2,3",
953 "CounterHTOff": "0,1,2,3,4,5,6,7",
962 "Counter": "0,1,2,3",
963 "CounterHTOff": "0,1,2,3,4,5,6,7",
971 "Counter": "0,1,2,3",
972 "CounterHTOff": "0,1,2,3,4,5,6,7",
981 "Counter": "0,1,2,3",
982 "CounterHTOff": "0,1,2,3,4,5,6,7",
990 "Counter": "0,1,2,3",
991 "CounterHTOff": "0,1,2,3,4,5,6,7",
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3,4,5,6,7",
1008 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
1009 "Counter": "0,1,2,3",
1010 "CounterHTOff": "0,1,2,3,4,5,6,7",
1018 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
1019 "Counter": "0,1,2,3",
1020 "CounterHTOff": "0,1,2,3,4,5,6,7",
1028 "Counter": "0,1,2,3",
1029 "CounterHTOff": "0,1,2,3,4,5,6,7",
1038 "Counter": "0,1,2,3",
1039 "CounterHTOff": "0,1,2,3,4,5,6,7",
1047 "Counter": "0,1,2,3",
1048 "CounterHTOff": "0,1,2,3,4,5,6,7",
1057 "Counter": "0,1,2,3",
1058 "CounterHTOff": "0,1,2,3,4,5,6,7",
1065 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1066 "Counter": "0,1,2,3",
1067 "CounterHTOff": "0,1,2,3,4,5,6,7",
1075 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1076 "Counter": "0,1,2,3",
1077 "CounterHTOff": "0,1,2,3,4,5,6,7",
1085 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1086 "Counter": "0,1,2,3",
1087 "CounterHTOff": "0,1,2,3,4,5,6,7",
1088 "CounterMask": "3",
1095 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1096 "Counter": "0,1,2,3",
1097 "CounterHTOff": "0,1,2,3,4,5,6,7",
1105 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1106 "Counter": "0,1,2,3",
1107 "CounterHTOff": "0,1,2,3,4,5,6,7",
1116 "Counter": "0,1,2,3",
1117 "CounterHTOff": "0,1,2,3,4,5,6,7",
1120 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1127 "Counter": "0,1,2,3",
1128 "CounterHTOff": "0,1,2,3",
1138 "Counter": "0,1,2,3",
1139 "CounterHTOff": "0,1,2,3",
1149 "Counter": "0,1,2,3",
1150 "CounterHTOff": "0,1,2,3,4,5,6,7",
1154 "PublicDescription": "This event counts the number of micro-ops retired.",
1160 "Counter": "0,1,2,3",
1161 "CounterHTOff": "0,1,2,3",
1171 "Counter": "0,1,2,3",
1172 "CounterHTOff": "0,1,2,3,4,5,6,7",
1176 …h cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in d…
1182 "Counter": "0,1,2,3",
1183 "CounterHTOff": "0,1,2,3",
1193 "Counter": "0,1,2,3",
1194 "CounterHTOff": "0,1,2,3",