Lines Matching full:loads

126 …tions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides wi…
130 …"BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the…
134 …loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; …
142 … operating system. This metric approximates the potential delay of demand loads missing the first-…
146 …metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they…
150 …metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they…
186 …cription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
190 …etric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache m…
194 …"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to …
198 …"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to…
234 …his metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
238 …es how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching ca…
258 …tric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
262 …tric estimates fraction of cycles while the memory subsystem was handling loads from local memory.…
266 …tric estimates fraction of cycles while the memory subsystem was handling loads from remote memory…
270 …tric estimates fraction of cycles while the memory subsystem was handling loads from remote memory…
274 …tric estimates fraction of cycles while the memory subsystem was handling loads from remote cache …
278 …tric estimates fraction of cycles while the memory subsystem was handling loads from remote cache …
412 … of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) S…
419 … of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) S…
672         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
678         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
684         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",