Lines Matching +full:3 +full:- +full:7
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "Counter": "0,1,2,3",
17 "CounterHTOff": "0,1,2,3,4,5,6,7",
26 "Counter": "0,1,2,3",
27 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "BriefDescription": "Speculative and retired macro-conditional branches",
36 "Counter": "0,1,2,3",
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
40 "PublicDescription": "Speculative and retired macro-conditional branches.",
45 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
46 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
50 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
56 "Counter": "0,1,2,3",
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
76 "Counter": "0,1,2,3",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
84 "BriefDescription": "Not taken macro-conditional branches",
85 "Counter": "0,1,2,3",
86 "CounterHTOff": "0,1,2,3,4,5,6,7",
89 "PublicDescription": "Not taken macro-conditional branches.",
94 "BriefDescription": "Taken speculative and retired macro-conditional branches",
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
99 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
104 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
105 "Counter": "0,1,2,3",
106 "CounterHTOff": "0,1,2,3,4,5,6,7",
109 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
115 "Counter": "0,1,2,3",
116 "CounterHTOff": "0,1,2,3,4,5,6,7",
125 "Counter": "0,1,2,3",
126 "CounterHTOff": "0,1,2,3,4,5,6,7",
135 "Counter": "0,1,2,3",
136 "CounterHTOff": "0,1,2,3,4,5,6,7",
145 "Counter": "0,1,2,3",
146 "CounterHTOff": "0,1,2,3,4,5,6,7",
155 "Counter": "0,1,2,3",
156 "CounterHTOff": "0,1,2,3,4,5,6,7",
164 "Counter": "0,1,2,3",
165 "CounterHTOff": "0,1,2,3",
174 "Counter": "0,1,2,3",
175 "CounterHTOff": "0,1,2,3,4,5,6,7",
184 "Counter": "0,1,2,3",
185 "CounterHTOff": "0,1,2,3,4,5,6,7",
194 "Counter": "0,1,2,3",
195 "CounterHTOff": "0,1,2,3,4,5,6,7",
203 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
204 "Counter": "0,1,2,3",
205 "CounterHTOff": "0,1,2,3,4,5,6,7",
214 "Counter": "0,1,2,3",
215 "CounterHTOff": "0,1,2,3,4,5,6,7",
224 "Counter": "0,1,2,3",
225 "CounterHTOff": "0,1,2,3,4,5,6,7",
234 "Counter": "0,1,2,3",
235 "CounterHTOff": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3",
245 "CounterHTOff": "0,1,2,3,4,5,6,7",
254 "Counter": "0,1,2,3",
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
264 "Counter": "0,1,2,3",
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
274 "Counter": "0,1,2,3",
275 "CounterHTOff": "0,1,2,3,4,5,6,7",
284 "Counter": "0,1,2,3",
285 "CounterHTOff": "0,1,2,3,4,5,6,7",
294 "Counter": "0,1,2,3",
295 "CounterHTOff": "0,1,2,3,4,5,6,7",
304 "Counter": "0,1,2,3",
305 "CounterHTOff": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3",
315 "CounterHTOff": "0,1,2,3,4,5,6,7",
324 "Counter": "0,1,2,3",
325 "CounterHTOff": "0,1,2,3,4,5,6,7",
333 "Counter": "0,1,2,3",
334 "CounterHTOff": "0,1,2,3",
343 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3,4,5,6,7",
353 "Counter": "0,1,2,3",
354 "CounterHTOff": "0,1,2,3,4,5,6,7",
363 "Counter": "0,1,2,3",
364 "CounterHTOff": "0,1,2,3",
372 "Counter": "0,1,2,3",
373 "CounterHTOff": "0,1,2,3,4,5,6,7",
383 "Counter": "0,1,2,3",
384 "CounterHTOff": "0,1,2,3,4,5,6,7",
392 "Counter": "0,1,2,3",
393 "CounterHTOff": "0,1,2,3,4,5,6,7",
409 "Counter": "0,1,2,3",
410 "CounterHTOff": "0,1,2,3,4,5,6,7",
420 "Counter": "0,1,2,3",
421 "CounterHTOff": "0,1,2,3,4,5,6,7",
447 "Counter": "0,1,2,3",
448 "CounterHTOff": "0,1,2,3,4,5,6,7",
457 "Counter": "0,1,2,3",
458 "CounterHTOff": "0,1,2,3,4,5,6,7",
487 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3,4,5,6,7",
497 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3,4,5,6,7",
508 "Counter": "0,1,2,3",
509 "CounterHTOff": "0,1,2,3",
519 "Counter": "0,1,2,3",
520 "CounterHTOff": "0,1,2,3",
529 "Counter": "0,1,2,3",
530 "CounterHTOff": "0,1,2,3",
561 "Counter": "0,1,2,3",
562 "CounterHTOff": "0,1,2,3",
571 "Counter": "0,1,2,3",
572 "CounterHTOff": "0,1,2,3",
582 "Counter": "0,1,2,3",
583 "CounterHTOff": "0,1,2,3",
592 "Counter": "0,1,2,3",
593 "CounterHTOff": "0,1,2,3",
602 "Counter": "0,1,2,3",
603 "CounterHTOff": "0,1,2,3",
612 "Counter": "0,1,2,3",
613 "CounterHTOff": "0,1,2,3,4,5,6,7",
622 "Counter": "0,1,2,3",
623 "CounterHTOff": "0,1,2,3,4,5,6,7",
638 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
639 "Counter": "0,1,2,3",
640 "CounterHTOff": "0,1,2,3,4,5,6,7",
659 "Counter": "0,1,2,3",
660 "CounterHTOff": "0,1,2,3,4,5,6,7",
670 "Counter": "0,1,2,3",
671 "CounterHTOff": "0,1,2,3,4,5,6,7",
680 "Counter": "0,1,2,3",
681 "CounterHTOff": "0,1,2,3,4,5,6,7",
691 "Counter": "0,1,2,3",
692 "CounterHTOff": "0,1,2,3,4,5,6,7",
700 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
701 "Counter": "0,1,2,3",
702 "CounterHTOff": "0,1,2,3,4,5,6,7",
711 "Counter": "0,1,2,3",
712 "CounterHTOff": "0,1,2,3,4,5,6,7",
720 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
721 "Counter": "0,1,2,3",
722 "CounterHTOff": "0,1,2,3,4,5,6,7",
725 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
730 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
731 "Counter": "0,1,2,3",
732 "CounterHTOff": "0,1,2,3,4,5,6,7",
735 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
741 "Counter": "0,1,2,3",
742 "CounterHTOff": "0,1,2,3,4,5,6,7",
752 "Counter": "0,1,2,3",
753 "CounterHTOff": "0,1,2,3,4,5,6,7",
763 "Counter": "0,1,2,3",
764 "CounterHTOff": "0,1,2,3,4,5,6,7",
772 "Counter": "0,1,2,3",
773 "CounterHTOff": "0,1,2,3,4,5,6,7",
783 "Counter": "0,1,2,3",
784 "CounterHTOff": "0,1,2,3,4,5,6,7",
792 "BriefDescription": "Self-modifying code (SMC) detected.",
793 "Counter": "0,1,2,3",
794 "CounterHTOff": "0,1,2,3,4,5,6,7",
797 "PublicDescription": "Number of self-modifying-code machine clears detected.",
803 "Counter": "0,1,2,3",
804 "CounterHTOff": "0,1,2,3,4,5,6,7",
812 "Counter": "0,1,2,3",
813 "CounterHTOff": "0,1,2,3,4,5,6,7",
821 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7",
829 "BriefDescription": "Resource-related stall cycles",
830 "Counter": "0,1,2,3",
831 "CounterHTOff": "0,1,2,3,4,5,6,7",
839 "BriefDescription": "Cycles stalled due to re-order buffer full.",
840 "Counter": "0,1,2,3",
841 "CounterHTOff": "0,1,2,3,4,5,6,7",
849 "Counter": "0,1,2,3",
850 "CounterHTOff": "0,1,2,3,4,5,6,7",
858 "Counter": "0,1,2,3",
859 "CounterHTOff": "0,1,2,3,4,5,6,7",
868 "Counter": "0,1,2,3",
869 "CounterHTOff": "0,1,2,3,4,5,6,7",
878 "Counter": "0,1,2,3",
879 "CounterHTOff": "0,1,2,3,4,5,6,7",
888 "Counter": "0,1,2,3",
889 "CounterHTOff": "0,1,2,3,4,5,6,7",
900 "Counter": "0,1,2,3",
901 "CounterHTOff": "0,1,2,3,4,5,6,7",
911 "Counter": "0,1,2,3",
912 "CounterHTOff": "0,1,2,3,4,5,6,7",
921 "Counter": "0,1,2,3",
922 "CounterHTOff": "0,1,2,3,4,5,6,7",
932 "Counter": "0,1,2,3",
933 "CounterHTOff": "0,1,2,3,4,5,6,7",
942 "Counter": "0,1,2,3",
943 "CounterHTOff": "0,1,2,3,4,5,6,7",
953 "Counter": "0,1,2,3",
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
961 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
962 "Counter": "0,1,2,3",
963 "CounterHTOff": "0,1,2,3,4,5,6,7",
966 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
972 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
973 "Counter": "0,1,2,3",
974 "CounterHTOff": "0,1,2,3,4,5,6,7",
977 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
983 "Counter": "0,1,2,3",
984 "CounterHTOff": "0,1,2,3,4,5,6,7",
994 "Counter": "0,1,2,3",
995 "CounterHTOff": "0,1,2,3,4,5,6,7",
1004 "Counter": "0,1,2,3",
1005 "CounterHTOff": "0,1,2,3,4,5,6,7",
1015 "Counter": "0,1,2,3",
1016 "CounterHTOff": "0,1,2,3,4,5,6,7",
1025 "Counter": "0,1,2,3",
1026 "CounterHTOff": "0,1,2,3,4,5,6,7",
1029 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
1034 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
1035 "Counter": "0,1,2,3",
1036 "CounterHTOff": "0,1,2,3,4,5,6,7",
1040 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1045 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1046 "Counter": "0,1,2,3",
1047 "CounterHTOff": "0,1,2,3,4,5,6,7",
1051 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1056 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1057 "Counter": "0,1,2,3",
1058 "CounterHTOff": "0,1,2,3,4,5,6,7",
1059 "CounterMask": "3",
1062 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1067 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1068 "Counter": "0,1,2,3",
1069 "CounterHTOff": "0,1,2,3,4,5,6,7",
1073 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1078 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1079 "Counter": "0,1,2,3",
1080 "CounterHTOff": "0,1,2,3,4,5,6,7",
1084 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1089 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1090 "Counter": "0,1,2,3",
1091 "CounterHTOff": "0,1,2,3,4,5,6,7",
1095 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1100 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1101 "Counter": "0,1,2,3",
1102 "CounterHTOff": "0,1,2,3,4,5,6,7",
1106 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1111 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1112 "Counter": "0,1,2,3",
1113 "CounterHTOff": "0,1,2,3,4,5,6,7",
1114 "CounterMask": "3",
1117 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1122 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1123 "Counter": "0,1,2,3",
1124 "CounterHTOff": "0,1,2,3,4,5,6,7",
1128 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1134 "Counter": "0,1,2,3",
1135 "CounterHTOff": "0,1,2,3",
1144 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1145 "Counter": "0,1,2,3",
1146 "CounterHTOff": "0,1,2,3,4,5,6,7",
1149 …"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask …
1155 "Counter": "0,1,2,3",
1156 "CounterHTOff": "0,1,2,3,4,5,6,7",
1166 "Counter": "0,1,2,3",
1167 "CounterHTOff": "0,1,2,3",
1177 "BriefDescription": "Number of flags-merge uops being allocated.",
1178 "Counter": "0,1,2,3",
1179 "CounterHTOff": "0,1,2,3,4,5,6,7",
1182 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
1188 "Counter": "0,1,2,3",
1189 "CounterHTOff": "0,1,2,3,4,5,6,7",
1197 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
1198 "Counter": "0,1,2,3",
1199 "CounterHTOff": "0,1,2,3,4,5,6,7",
1202 …"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2…
1208 "Counter": "0,1,2,3",
1209 "CounterHTOff": "0,1,2,3",
1220 "Counter": "0,1,2,3",
1221 "CounterHTOff": "0,1,2,3,4,5,6,7",
1231 "Counter": "0,1,2,3",
1232 "CounterHTOff": "0,1,2,3",
1242 "Counter": "0,1,2,3",
1243 "CounterHTOff": "0,1,2,3,4,5,6,7",
1252 "Counter": "0,1,2,3",
1253 "CounterHTOff": "0,1,2,3",
1263 "Counter": "0,1,2,3",
1264 "CounterHTOff": "0,1,2,3",