Lines Matching +full:3 +full:- +full:7
5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
18 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
30 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
57 "PEBScounters": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5,6,7",
69 "PEBScounters": "0,1,2,3,4,5,6,7",
77 "Counter": "0,1,2,3,4,5,6,7",
81 "PEBScounters": "0,1,2,3,4,5,6,7",
89 "Counter": "0,1,2,3,4,5,6,7",
93 "PEBScounters": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
105 "PEBScounters": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3,4,5,6,7",
117 "PEBScounters": "0,1,2,3,4,5,6,7",
125 "Counter": "0,1,2,3,4,5,6,7",
129 "PEBScounters": "0,1,2,3,4,5,6,7",
137 "Counter": "0,1,2,3,4,5,6,7",
141 "PEBScounters": "0,1,2,3,4,5,6,7",
148 "Counter": "0,1,2,3,4,5,6,7",
152 "PEBScounters": "0,1,2,3,4,5,6,7",
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
160 "Counter": "0,1,2,3,4,5,6,7",
164 "PEBScounters": "0,1,2,3,4,5,6,7",
172 "Counter": "0,1,2,3,4,5,6,7",
176 "PEBScounters": "0,1,2,3,4,5,6,7",
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
184 "Counter": "0,1,2,3,4,5,6,7",
188 "PEBScounters": "0,1,2,3,4,5,6,7",
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
196 "Counter": "0,1,2,3,4,5,6,7",
200 "PEBScounters": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
212 "PEBScounters": "0,1,2,3,4,5,6,7",
220 "Counter": "0,1,2,3,4,5,6,7",
224 "PEBScounters": "0,1,2,3,4,5,6,7",
225 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
232 "Counter": "0,1,2,3,4,5,6,7",
235 "PEBScounters": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3,4,5,6,7",
247 "PEBScounters": "0,1,2,3,4,5,6,7",
256 "Counter": "0,1,2,3,4,5,6,7",
259 "PEBScounters": "0,1,2,3,4,5,6,7",
260 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
279 "Counter": "0,1,2,3,4,5,6,7",
282 "PEBScounters": "0,1,2,3,4,5,6,7",
302 "Counter": "0,1,2,3,4,5,6,7",
305 "PEBScounters": "0,1,2,3,4,5,6,7",
313 "Counter": "0,1,2,3",
317 "PEBScounters": "0,1,2,3",
325 "Counter": "0,1,2,3",
329 "PEBScounters": "0,1,2,3",
337 "Counter": "0,1,2,3,4,5,6,7",
341 "PEBScounters": "0,1,2,3,4,5,6,7",
349 "Counter": "0,1,2,3",
353 "PEBScounters": "0,1,2,3",
361 "Counter": "0,1,2,3",
365 "PEBScounters": "0,1,2,3",
373 "Counter": "0,1,2,3,4,5,6,7",
377 "PEBScounters": "0,1,2,3,4,5,6,7",
385 "Counter": "0,1,2,3,4,5,6,7",
389 "PEBScounters": "0,1,2,3,4,5,6,7",
397 "Counter": "0,1,2,3,4,5,6,7",
400 "PEBScounters": "0,1,2,3,4,5,6,7",
409 "Counter": "0,1,2,3,4,5,6,7",
412 "PEBScounters": "0,1,2,3,4,5,6,7",
419 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
421 "Counter": "0,1,2,3,4,5,6,7",
423 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
424 "PEBScounters": "0,1,2,3,4,5,6,7",
425 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
433 "Counter": "0,1,2,3,4,5,6,7",
436 "PEBScounters": "0,1,2,3,4,5,6,7",
445 "Counter": "0,1,2,3,4,5,6,7",
449 "PEBScounters": "0,1,2,3,4,5,6,7",
458 "Counter": "0,1,2,3",
461 "PEBScounters": "0,1,2,3",
462 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
470 "Counter": "0,1,2,3",
473 "PEBScounters": "0,1,2,3",
480 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
486 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
491 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
493 "Counter": "0,1,2,3,4,5,6,7",
497 "PEBScounters": "0,1,2,3,4,5,6,7",
498 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
504 "Counter": "0,1,2,3,4,5,6,7",
508 "PEBScounters": "0,1,2,3,4,5,6,7",
524 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
526 "Counter": "0,1,2,3,4,5,6,7",
530 "PEBScounters": "0,1,2,3,4,5,6,7",
531 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
539 "Counter": "0,1,2,3,4,5,6,7",
542 "PEBScounters": "0,1,2,3,4,5,6,7",
551 "Counter": "0,1,2,3,4,5,6,7",
554 "PEBScounters": "0,1,2,3,4,5,6,7",
563 "Counter": "0,1,2,3,4,5,6,7",
566 "PEBScounters": "0,1,2,3,4,5,6,7",
567 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
575 "Counter": "0,1,2,3",
578 "PEBScounters": "0,1,2,3",
587 "Counter": "0,1,2,3",
590 "PEBScounters": "0,1,2,3",
599 "Counter": "0,1,2,3",
602 "PEBScounters": "0,1,2,3",
611 "Counter": "0,1,2,3",
614 "PEBScounters": "0,1,2,3",
615 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
623 "Counter": "0,1,2,3",
627 "PEBScounters": "0,1,2,3",
628 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
636 "Counter": "0,1,2,3",
640 "PEBScounters": "0,1,2,3",
641 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
649 "Counter": "0,1,2,3",
652 "PEBScounters": "0,1,2,3",
653 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
661 "Counter": "0,1,2,3,4,5,6,7",
666 "PEBScounters": "0,1,2,3,4,5,6,7",
673 "BriefDescription": "Self-modifying code (SMC) detected.",
675 "Counter": "0,1,2,3,4,5,6,7",
678 "PEBScounters": "0,1,2,3,4,5,6,7",
679 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
687 "Counter": "0,1,2,3,4,5,6,7",
690 "PEBScounters": "0,1,2,3,4,5,6,7",
698 "Counter": "0,1,2,3,4,5,6,7",
708 "Counter": "0,1,2,3,4,5,6,7",
711 "PEBScounters": "0,1,2,3,4,5,6,7",
712 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
720 "Counter": "0,1,2,3,4,5,6,7",
723 "PEBScounters": "0,1,2,3,4,5,6,7",
731 "Counter": "0,1,2,3,4,5,6,7",
734 "PEBScounters": "0,1,2,3,4,5,6,7",
735 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
743 "Counter": "0,1,2,3,4,5,6,7",
749 "PEBScounters": "0,1,2,3,4,5,6,7",
750 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
756 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
758 "Counter": "0,1,2,3,4,5,6,7",
761 "PEBScounters": "0,1,2,3,4,5,6,7",
762 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
768 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
770 "Counter": "Fixed counter 3",
773 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
779 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
781 "Counter": "0,1,2,3,4,5,6,7",
784 "PEBScounters": "0,1,2,3,4,5,6,7",
785 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
793 "Counter": "0,1,2,3",
796 "PEBScounters": "0,1,2,3",
805 "Counter": "0,1,2,3,4,5,6,7",
808 "PEBScounters": "0,1,2,3,4,5,6,7",
809 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
817 "Counter": "0,1,2,3,4,5,6,7",
820 "PEBScounters": "0,1,2,3,4,5,6,7",
821 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
827 "BriefDescription": "Number of uops executed on port 2 and 3",
829 "Counter": "0,1,2,3,4,5,6,7",
832 "PEBScounters": "0,1,2,3,4,5,6,7",
833 …Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reser…
841 "Counter": "0,1,2,3,4,5,6,7",
844 "PEBScounters": "0,1,2,3,4,5,6,7",
845 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
853 "Counter": "0,1,2,3,4,5,6,7",
856 "PEBScounters": "0,1,2,3,4,5,6,7",
857 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
865 "Counter": "0,1,2,3,4,5,6,7",
868 "PEBScounters": "0,1,2,3,4,5,6,7",
869 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
875 "BriefDescription": "Number of uops executed on port 7 and 8",
877 "Counter": "0,1,2,3,4,5,6,7",
880 "PEBScounters": "0,1,2,3,4,5,6,7",
881 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
887 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
889 "Counter": "0,1,2,3,4,5,6,7",
893 "PEBScounters": "0,1,2,3,4,5,6,7",
894 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
900 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
902 "Counter": "0,1,2,3,4,5,6,7",
906 "PEBScounters": "0,1,2,3,4,5,6,7",
907 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
913 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
915 "Counter": "0,1,2,3,4,5,6,7",
916 "CounterMask": "3",
919 "PEBScounters": "0,1,2,3,4,5,6,7",
920 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
926 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
928 "Counter": "0,1,2,3,4,5,6,7",
932 "PEBScounters": "0,1,2,3,4,5,6,7",
933 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
939 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
941 "Counter": "0,1,2,3,4,5,6,7",
945 "PEBScounters": "0,1,2,3,4,5,6,7",
946 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
952 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
954 "Counter": "0,1,2,3,4,5,6,7",
958 "PEBScounters": "0,1,2,3,4,5,6,7",
959 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
965 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
967 "Counter": "0,1,2,3,4,5,6,7",
968 "CounterMask": "3",
971 "PEBScounters": "0,1,2,3,4,5,6,7",
972 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
978 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
980 "Counter": "0,1,2,3,4,5,6,7",
984 "PEBScounters": "0,1,2,3,4,5,6,7",
985 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
993 "Counter": "0,1,2,3,4,5,6,7",
998 "PEBScounters": "0,1,2,3,4,5,6,7",
1005 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1007 "Counter": "0,1,2,3,4,5,6,7",
1010 "PEBScounters": "0,1,2,3,4,5,6,7",
1018 "Counter": "0,1,2,3,4,5,6,7",
1021 "PEBScounters": "0,1,2,3,4,5,6,7",
1030 "Counter": "0,1,2,3,4,5,6,7",
1033 "PEBScounters": "0,1,2,3,4,5,6,7",
1042 "Counter": "0,1,2,3,4,5,6,7",
1047 "PEBScounters": "0,1,2,3,4,5,6,7",
1054 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1056 "Counter": "0,1,2,3,4,5,6,7",
1059 "PEBScounters": "0,1,2,3,4,5,6,7",
1060 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1068 "Counter": "0,1,2,3,4,5,6,7",
1071 "PEBScounters": "0,1,2,3,4,5,6,7",
1079 "Counter": "0,1,2,3,4,5,6,7",
1084 "PEBScounters": "0,1,2,3,4,5,6,7",
1093 "Counter": "0,1,2,3,4,5,6,7",
1098 "PEBScounters": "0,1,2,3,4,5,6,7",