Lines Matching +full:0 +full:- +full:7
5 "Counter": "0,1,2,3,4,5,6,7",
7 "EventCode": "0x14",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 "UMask": "0x9"
18 "Counter": "0,1,2,3,4,5,6,7",
19 "EventCode": "0xc1",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
25 "UMask": "0x7"
30 "Counter": "0,1,2,3,4,5,6,7",
31 "EventCode": "0xc4",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
42 "EventCode": "0xc4",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
48 "UMask": "0x11"
53 "Counter": "0,1,2,3,4,5,6,7",
54 "EventCode": "0xc4",
57 "PEBScounters": "0,1,2,3,4,5,6,7",
60 "UMask": "0x10"
65 "Counter": "0,1,2,3,4,5,6,7",
66 "EventCode": "0xc4",
69 "PEBScounters": "0,1,2,3,4,5,6,7",
72 "UMask": "0x1"
77 "Counter": "0,1,2,3,4,5,6,7",
78 "EventCode": "0xc4",
81 "PEBScounters": "0,1,2,3,4,5,6,7",
84 "UMask": "0x40"
89 "Counter": "0,1,2,3,4,5,6,7",
90 "EventCode": "0xc4",
93 "PEBScounters": "0,1,2,3,4,5,6,7",
96 "UMask": "0x80"
101 "Counter": "0,1,2,3,4,5,6,7",
102 "EventCode": "0xc4",
105 "PEBScounters": "0,1,2,3,4,5,6,7",
108 "UMask": "0x2"
113 "Counter": "0,1,2,3,4,5,6,7",
114 "EventCode": "0xc4",
117 "PEBScounters": "0,1,2,3,4,5,6,7",
120 "UMask": "0x8"
125 "Counter": "0,1,2,3,4,5,6,7",
126 "EventCode": "0xc4",
129 "PEBScounters": "0,1,2,3,4,5,6,7",
132 "UMask": "0x20"
137 "Counter": "0,1,2,3,4,5,6,7",
138 "EventCode": "0xc5",
141 "PEBScounters": "0,1,2,3,4,5,6,7",
148 "Counter": "0,1,2,3,4,5,6,7",
149 "EventCode": "0xc5",
152 "PEBScounters": "0,1,2,3,4,5,6,7",
155 "UMask": "0x11"
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
160 "Counter": "0,1,2,3,4,5,6,7",
161 "EventCode": "0xc5",
164 "PEBScounters": "0,1,2,3,4,5,6,7",
167 "UMask": "0x10"
172 "Counter": "0,1,2,3,4,5,6,7",
173 "EventCode": "0xc5",
176 "PEBScounters": "0,1,2,3,4,5,6,7",
179 "UMask": "0x1"
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
184 "Counter": "0,1,2,3,4,5,6,7",
185 "EventCode": "0xc5",
188 "PEBScounters": "0,1,2,3,4,5,6,7",
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
191 "UMask": "0x80"
196 "Counter": "0,1,2,3,4,5,6,7",
197 "EventCode": "0xc5",
200 "PEBScounters": "0,1,2,3,4,5,6,7",
203 "UMask": "0x2"
208 "Counter": "0,1,2,3,4,5,6,7",
209 "EventCode": "0xc5",
212 "PEBScounters": "0,1,2,3,4,5,6,7",
215 "UMask": "0x20"
220 "Counter": "0,1,2,3,4,5,6,7",
221 "EventCode": "0xc5",
224 "PEBScounters": "0,1,2,3,4,5,6,7",
225 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
227 "UMask": "0x8"
232 "Counter": "0,1,2,3,4,5,6,7",
233 "EventCode": "0xec",
235 "PEBScounters": "0,1,2,3,4,5,6,7",
239 "UMask": "0x2"
244 "Counter": "0,1,2,3,4,5,6,7",
245 "EventCode": "0x3C",
247 "PEBScounters": "0,1,2,3,4,5,6,7",
251 "UMask": "0x2"
256 "Counter": "0,1,2,3,4,5,6,7",
257 "EventCode": "0x3c",
259 "PEBScounters": "0,1,2,3,4,5,6,7",
260 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
263 "UMask": "0x8"
274 "UMask": "0x3"
279 "Counter": "0,1,2,3,4,5,6,7",
280 "EventCode": "0x3C",
282 "PEBScounters": "0,1,2,3,4,5,6,7",
286 "UMask": "0x1"
297 "UMask": "0x2"
302 "Counter": "0,1,2,3,4,5,6,7",
303 "EventCode": "0x3C",
305 "PEBScounters": "0,1,2,3,4,5,6,7",
313 "Counter": "0,1,2,3",
315 "EventCode": "0xA3",
317 "PEBScounters": "0,1,2,3",
320 "UMask": "0x8"
325 "Counter": "0,1,2,3",
327 "EventCode": "0xA3",
329 "PEBScounters": "0,1,2,3",
332 "UMask": "0x1"
337 "Counter": "0,1,2,3,4,5,6,7",
339 "EventCode": "0xA3",
341 "PEBScounters": "0,1,2,3,4,5,6,7",
344 "UMask": "0x10"
349 "Counter": "0,1,2,3",
351 "EventCode": "0xA3",
353 "PEBScounters": "0,1,2,3",
356 "UMask": "0xc"
361 "Counter": "0,1,2,3",
363 "EventCode": "0xa3",
365 "PEBScounters": "0,1,2,3",
368 "UMask": "0x5"
373 "Counter": "0,1,2,3,4,5,6,7",
375 "EventCode": "0xa3",
377 "PEBScounters": "0,1,2,3,4,5,6,7",
380 "UMask": "0x14"
385 "Counter": "0,1,2,3,4,5,6,7",
387 "EventCode": "0xa3",
389 "PEBScounters": "0,1,2,3,4,5,6,7",
392 "UMask": "0x4"
397 "Counter": "0,1,2,3,4,5,6,7",
398 "EventCode": "0xa6",
400 "PEBScounters": "0,1,2,3,4,5,6,7",
404 "UMask": "0x2"
409 "Counter": "0,1,2,3,4,5,6,7",
410 "EventCode": "0xa6",
412 "PEBScounters": "0,1,2,3,4,5,6,7",
416 "UMask": "0x4"
421 "Counter": "0,1,2,3,4,5,6,7",
422 "EventCode": "0xa6",
424 "PEBScounters": "0,1,2,3,4,5,6,7",
428 "UMask": "0x8"
433 "Counter": "0,1,2,3,4,5,6,7",
434 "EventCode": "0xa6",
436 "PEBScounters": "0,1,2,3,4,5,6,7",
440 "UMask": "0x10"
445 "Counter": "0,1,2,3,4,5,6,7",
447 "EventCode": "0xA6",
449 "PEBScounters": "0,1,2,3,4,5,6,7",
453 "UMask": "0x40"
458 "Counter": "0,1,2,3",
459 "EventCode": "0x87",
461 "PEBScounters": "0,1,2,3",
462 …0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the num…
465 "UMask": "0x1"
470 "Counter": "0,1,2,3",
471 "EventCode": "0x55",
473 "PEBScounters": "0,1,2,3",
477 "UMask": "0x1"
480 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
482 "Counter": "Fixed counter 0",
486 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
488 "UMask": "0x1"
491 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
493 "Counter": "0,1,2,3,4,5,6,7",
494 "EventCode": "0xc0",
497 "PEBScounters": "0,1,2,3,4,5,6,7",
498 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
504 "Counter": "0,1,2,3,4,5,6,7",
505 "EventCode": "0xc0",
508 "PEBScounters": "0,1,2,3,4,5,6,7",
510 "UMask": "0x2"
515 "Counter": "Fixed counter 0",
519 …R) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
521 "UMask": "0x1"
524 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
526 "Counter": "0,1,2,3,4,5,6,7",
528 "EventCode": "0x0D",
530 "PEBScounters": "0,1,2,3,4,5,6,7",
531 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
534 "UMask": "0x3"
539 "Counter": "0,1,2,3,4,5,6,7",
540 "EventCode": "0x0d",
542 "PEBScounters": "0,1,2,3,4,5,6,7",
546 "UMask": "0x80"
551 "Counter": "0,1,2,3,4,5,6,7",
552 "EventCode": "0x0D",
554 "PEBScounters": "0,1,2,3,4,5,6,7",
558 "UMask": "0x1"
563 "Counter": "0,1,2,3,4,5,6,7",
564 "EventCode": "0x0d",
566 "PEBScounters": "0,1,2,3,4,5,6,7",
567 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
570 "UMask": "0x10"
575 "Counter": "0,1,2,3",
576 "EventCode": "0x03",
578 "PEBScounters": "0,1,2,3",
582 "UMask": "0x8"
587 "Counter": "0,1,2,3",
588 "EventCode": "0x03",
590 "PEBScounters": "0,1,2,3",
594 "UMask": "0x2"
599 "Counter": "0,1,2,3",
600 "EventCode": "0x07",
602 "PEBScounters": "0,1,2,3",
606 "UMask": "0x1"
611 "Counter": "0,1,2,3",
612 "EventCode": "0x4c",
614 "PEBScounters": "0,1,2,3",
615 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
618 "UMask": "0x1"
623 "Counter": "0,1,2,3",
625 "EventCode": "0xA8",
627 "PEBScounters": "0,1,2,3",
628 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
631 "UMask": "0x1"
636 "Counter": "0,1,2,3",
638 "EventCode": "0xa8",
640 "PEBScounters": "0,1,2,3",
641 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
644 "UMask": "0x1"
649 "Counter": "0,1,2,3",
650 "EventCode": "0xa8",
652 "PEBScounters": "0,1,2,3",
653 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
656 "UMask": "0x1"
661 "Counter": "0,1,2,3,4,5,6,7",
664 "EventCode": "0xc3",
666 "PEBScounters": "0,1,2,3,4,5,6,7",
670 "UMask": "0x1"
673 "BriefDescription": "Self-modifying code (SMC) detected.",
675 "Counter": "0,1,2,3,4,5,6,7",
676 "EventCode": "0xc3",
678 "PEBScounters": "0,1,2,3,4,5,6,7",
679 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
682 "UMask": "0x4"
687 "Counter": "0,1,2,3,4,5,6,7",
688 "EventCode": "0xcc",
690 "PEBScounters": "0,1,2,3,4,5,6,7",
693 "UMask": "0x20"
698 "Counter": "0,1,2,3,4,5,6,7",
699 "EventCode": "0xcc",
703 "UMask": "0x40"
708 "Counter": "0,1,2,3,4,5,6,7",
709 "EventCode": "0xa2",
711 "PEBScounters": "0,1,2,3,4,5,6,7",
712 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
715 "UMask": "0x8"
720 "Counter": "0,1,2,3,4,5,6,7",
721 "EventCode": "0xa2",
723 "PEBScounters": "0,1,2,3,4,5,6,7",
726 "UMask": "0x2"
731 "Counter": "0,1,2,3,4,5,6,7",
732 "EventCode": "0x5e",
734 "PEBScounters": "0,1,2,3,4,5,6,7",
735 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
738 "UMask": "0x1"
743 "Counter": "0,1,2,3,4,5,6,7",
746 "EventCode": "0x5E",
749 "PEBScounters": "0,1,2,3,4,5,6,7",
750 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
753 "UMask": "0x1"
756 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
758 "Counter": "0,1,2,3,4,5,6,7",
759 "EventCode": "0xa4",
761 "PEBScounters": "0,1,2,3,4,5,6,7",
762 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
765 "UMask": "0x2"
768 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
773 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
776 "UMask": "0x4"
779 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
781 "Counter": "0,1,2,3,4,5,6,7",
782 "EventCode": "0xa4",
784 "PEBScounters": "0,1,2,3,4,5,6,7",
785 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
788 "UMask": "0x1"
791 … "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
793 "Counter": "0,1,2,3",
794 "EventCode": "0x56",
796 "PEBScounters": "0,1,2,3",
797 "PublicDescription": "Uops exclusively fetched by decoder 0",
800 "UMask": "0x1"
803 "BriefDescription": "Number of uops executed on port 0",
805 "Counter": "0,1,2,3,4,5,6,7",
806 "EventCode": "0xa1",
808 "PEBScounters": "0,1,2,3,4,5,6,7",
809 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
812 "UMask": "0x1"
817 "Counter": "0,1,2,3,4,5,6,7",
818 "EventCode": "0xa1",
820 "PEBScounters": "0,1,2,3,4,5,6,7",
821 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
824 "UMask": "0x2"
829 "Counter": "0,1,2,3,4,5,6,7",
830 "EventCode": "0xa1",
832 "PEBScounters": "0,1,2,3,4,5,6,7",
833 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
836 "UMask": "0x4"
841 "Counter": "0,1,2,3,4,5,6,7",
842 "EventCode": "0xa1",
844 "PEBScounters": "0,1,2,3,4,5,6,7",
845 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
848 "UMask": "0x10"
853 "Counter": "0,1,2,3,4,5,6,7",
854 "EventCode": "0xa1",
856 "PEBScounters": "0,1,2,3,4,5,6,7",
857 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
860 "UMask": "0x20"
865 "Counter": "0,1,2,3,4,5,6,7",
866 "EventCode": "0xa1",
868 "PEBScounters": "0,1,2,3,4,5,6,7",
869 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
872 "UMask": "0x40"
875 "BriefDescription": "Number of uops executed on port 7 and 8",
877 "Counter": "0,1,2,3,4,5,6,7",
878 "EventCode": "0xa1",
880 "PEBScounters": "0,1,2,3,4,5,6,7",
881 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
884 "UMask": "0x80"
887 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
889 "Counter": "0,1,2,3,4,5,6,7",
891 "EventCode": "0xB1",
893 "PEBScounters": "0,1,2,3,4,5,6,7",
894 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
897 "UMask": "0x2"
900 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
902 "Counter": "0,1,2,3,4,5,6,7",
904 "EventCode": "0xB1",
906 "PEBScounters": "0,1,2,3,4,5,6,7",
907 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
910 "UMask": "0x2"
913 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
915 "Counter": "0,1,2,3,4,5,6,7",
917 "EventCode": "0xB1",
919 "PEBScounters": "0,1,2,3,4,5,6,7",
920 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
923 "UMask": "0x2"
926 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
928 "Counter": "0,1,2,3,4,5,6,7",
930 "EventCode": "0xB1",
932 "PEBScounters": "0,1,2,3,4,5,6,7",
933 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
936 "UMask": "0x2"
939 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
941 "Counter": "0,1,2,3,4,5,6,7",
943 "EventCode": "0xb1",
945 "PEBScounters": "0,1,2,3,4,5,6,7",
946 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
949 "UMask": "0x1"
952 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
954 "Counter": "0,1,2,3,4,5,6,7",
956 "EventCode": "0xb1",
958 "PEBScounters": "0,1,2,3,4,5,6,7",
959 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
962 "UMask": "0x1"
965 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
967 "Counter": "0,1,2,3,4,5,6,7",
969 "EventCode": "0xb1",
971 "PEBScounters": "0,1,2,3,4,5,6,7",
972 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
975 "UMask": "0x1"
978 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
980 "Counter": "0,1,2,3,4,5,6,7",
982 "EventCode": "0xb1",
984 "PEBScounters": "0,1,2,3,4,5,6,7",
985 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
988 "UMask": "0x1"
993 "Counter": "0,1,2,3,4,5,6,7",
995 "EventCode": "0xB1",
998 "PEBScounters": "0,1,2,3,4,5,6,7",
1002 "UMask": "0x1"
1005 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1007 "Counter": "0,1,2,3,4,5,6,7",
1008 "EventCode": "0xb1",
1010 "PEBScounters": "0,1,2,3,4,5,6,7",
1013 "UMask": "0x1"
1018 "Counter": "0,1,2,3,4,5,6,7",
1019 "EventCode": "0xB1",
1021 "PEBScounters": "0,1,2,3,4,5,6,7",
1025 "UMask": "0x10"
1030 "Counter": "0,1,2,3,4,5,6,7",
1031 "EventCode": "0x0e",
1033 "PEBScounters": "0,1,2,3,4,5,6,7",
1037 "UMask": "0x1"
1042 "Counter": "0,1,2,3,4,5,6,7",
1044 "EventCode": "0x0E",
1047 "PEBScounters": "0,1,2,3,4,5,6,7",
1051 "UMask": "0x1"
1054 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1056 "Counter": "0,1,2,3,4,5,6,7",
1057 "EventCode": "0x0e",
1059 "PEBScounters": "0,1,2,3,4,5,6,7",
1060 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1063 "UMask": "0x2"
1068 "Counter": "0,1,2,3,4,5,6,7",
1069 "EventCode": "0xc2",
1071 "PEBScounters": "0,1,2,3,4,5,6,7",
1074 "UMask": "0x2"
1079 "Counter": "0,1,2,3,4,5,6,7",
1081 "EventCode": "0xc2",
1084 "PEBScounters": "0,1,2,3,4,5,6,7",
1088 "UMask": "0x2"
1093 "Counter": "0,1,2,3,4,5,6,7",
1095 "EventCode": "0xc2",
1098 "PEBScounters": "0,1,2,3,4,5,6,7",
1101 "UMask": "0x2"