Lines Matching +full:high +full:- +full:bandwidth

4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
91 …": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
95bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for ca…
100 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
103 …re-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long i…
107 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
108 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
115 "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / CLKS",
122 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
130 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
133 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
141 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
146 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
149-of-order portion of the machine needs to recover its state after the clear. For example; this can…
154 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
157-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
165 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
170 … "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
173high latency even though it is being satisfied by the L1. Another example is loads who miss in the…
178 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
181-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
185 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
186 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
192 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
203 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
208 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LO…
215 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
219 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
227 …d re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW o…
235 …isfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 ca…
240 …ISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
248 "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
263 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
264 … (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.…
267 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
279 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
283 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
288 …MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_b…
295 … cycles where the core's performance was likely hurt due to approaching bandwidth limits of extern…
299bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-c…
304 …CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
323 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
331 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
335 … on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge…
336- ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.…
339 … on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge…
343 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
347 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
352 …tricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STO…
355-of-order core performance; however; holding resources for longer time can lead into undesired imp…
363 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
371 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
379 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
383 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
387-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
391 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
392 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
405 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
406 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
409-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
421 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
422 …PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
425-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
430 …k\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
433 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
437 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
441 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
465-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
473 …cal Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options…
535 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
538 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
542 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
543 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
546-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
550 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
554-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
562 …FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferabl…
566 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
570 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
574 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
578 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
582 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
586 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
590 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
594 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
598 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
602 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
606 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
624 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
628 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
629 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_in…
635 …tric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructio…
636 …"MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0…
639 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
644 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
647 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
663 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
668 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
671 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
681 … "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
687 … "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
693 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
699 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
700 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
705 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
711 … "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
712- tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_ica…
741 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
747 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
753 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
759 "BriefDescription": "The ratio of Executed- by Issued-Uops",
763 …iption": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions…
766 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
778 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
782-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
785 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
791 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
792 …"MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilizati…
852 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
856 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
859 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
863 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
866 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
870 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
873 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
877 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
880 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
884 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
911 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
923 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
929 …"BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_F…
935 …"BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means highe…
941 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
947 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
953 "BriefDescription": "Fraction of branches that are non-taken conditionals",
972 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
978 "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
983 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
989 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1014 …"MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS…
1037 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1050 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1056 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1062 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1068 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1086 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1092 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1098 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1104 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1126 … supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
1135 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1139 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
1142 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1146 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
1149 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1153 …e the core was running with power-delivery for license level 2 (introduced in SKX). This includes…
1157 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_o…
1174 "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
1192 …cy of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads …
1198 …o external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
1204 "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
1210 "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
1216 "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
1222 "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
1241 "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
1247 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
1253 "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
1259 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
1445 … "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
1452 "BriefDescription": "DDR memory read bandwidth (MB/sec)",
1459 "BriefDescription": "DDR memory write bandwidth (MB/sec)",
1466 "BriefDescription": "DDR memory bandwidth (MB/sec)",
1473 … "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
1480 … "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
1487 "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
1494 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
1501 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
1515 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
1529 …"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and …
1536 …"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and…
1543 …"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and …
1550 …"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and…
1558 …"MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / …