Lines Matching +full:0 +full:- +full:7
5 "Counter": "0,1,2,3,4,5,6,7",
7 "EventCode": "0x14",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 "UMask": "0x9"
18 "Counter": "0,1,2,3,4,5,6,7",
19 "EventCode": "0xc1",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
25 "UMask": "0x7"
30 "Counter": "0,1,2,3,4,5,6,7",
31 "EventCode": "0xc4",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
42 "EventCode": "0xc4",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
48 "UMask": "0x11"
53 "Counter": "0,1,2,3,4,5,6,7",
54 "EventCode": "0xc4",
57 "PEBScounters": "0,1,2,3,4,5,6,7",
60 "UMask": "0x10"
65 "Counter": "0,1,2,3,4,5,6,7",
66 "EventCode": "0xc4",
69 "PEBScounters": "0,1,2,3,4,5,6,7",
72 "UMask": "0x1"
77 "Counter": "0,1,2,3,4,5,6,7",
78 "EventCode": "0xc4",
81 "PEBScounters": "0,1,2,3,4,5,6,7",
84 "UMask": "0x40"
89 "Counter": "0,1,2,3,4,5,6,7",
90 "EventCode": "0xc4",
93 "PEBScounters": "0,1,2,3,4,5,6,7",
96 "UMask": "0x80"
101 "Counter": "0,1,2,3,4,5,6,7",
102 "EventCode": "0xc4",
105 "PEBScounters": "0,1,2,3,4,5,6,7",
108 "UMask": "0x2"
113 "Counter": "0,1,2,3,4,5,6,7",
114 "EventCode": "0xc4",
117 "PEBScounters": "0,1,2,3,4,5,6,7",
120 "UMask": "0x8"
125 "Counter": "0,1,2,3,4,5,6,7",
126 "EventCode": "0xc4",
129 "PEBScounters": "0,1,2,3,4,5,6,7",
132 "UMask": "0x20"
137 "Counter": "0,1,2,3,4,5,6,7",
138 "EventCode": "0xc5",
141 "PEBScounters": "0,1,2,3,4,5,6,7",
148 "Counter": "0,1,2,3,4,5,6,7",
149 "EventCode": "0xc5",
152 "PEBScounters": "0,1,2,3,4,5,6,7",
155 "UMask": "0x11"
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
160 "Counter": "0,1,2,3,4,5,6,7",
161 "EventCode": "0xc5",
164 "PEBScounters": "0,1,2,3,4,5,6,7",
167 "UMask": "0x10"
172 "Counter": "0,1,2,3,4,5,6,7",
173 "EventCode": "0xc5",
176 "PEBScounters": "0,1,2,3,4,5,6,7",
179 "UMask": "0x1"
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
184 "Counter": "0,1,2,3,4,5,6,7",
185 "EventCode": "0xc5",
188 "PEBScounters": "0,1,2,3,4,5,6,7",
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
191 "UMask": "0x80"
196 "Counter": "0,1,2,3,4,5,6,7",
197 "EventCode": "0xc5",
200 "PEBScounters": "0,1,2,3,4,5,6,7",
203 "UMask": "0x2"
208 "Counter": "0,1,2,3,4,5,6,7",
209 "EventCode": "0xc5",
212 "PEBScounters": "0,1,2,3,4,5,6,7",
215 "UMask": "0x20"
220 "Counter": "0,1,2,3,4,5,6,7",
221 "EventCode": "0xec",
223 "PEBScounters": "0,1,2,3,4,5,6,7",
227 "UMask": "0x2"
232 "Counter": "0,1,2,3,4,5,6,7",
233 "EventCode": "0x3C",
235 "PEBScounters": "0,1,2,3,4,5,6,7",
239 "UMask": "0x2"
244 "Counter": "0,1,2,3,4,5,6,7",
245 "EventCode": "0x3c",
247 "PEBScounters": "0,1,2,3,4,5,6,7",
248 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
251 "UMask": "0x8"
262 "UMask": "0x3"
267 "Counter": "0,1,2,3,4,5,6,7",
268 "EventCode": "0x3C",
270 "PEBScounters": "0,1,2,3,4,5,6,7",
274 "UMask": "0x1"
285 "UMask": "0x2"
290 "Counter": "0,1,2,3,4,5,6,7",
291 "EventCode": "0x3C",
293 "PEBScounters": "0,1,2,3,4,5,6,7",
301 "Counter": "0,1,2,3",
303 "EventCode": "0xA3",
305 "PEBScounters": "0,1,2,3",
308 "UMask": "0x8"
313 "Counter": "0,1,2,3",
315 "EventCode": "0xA3",
317 "PEBScounters": "0,1,2,3",
320 "UMask": "0x1"
325 "Counter": "0,1,2,3,4,5,6,7",
327 "EventCode": "0xA3",
329 "PEBScounters": "0,1,2,3,4,5,6,7",
332 "UMask": "0x10"
337 "Counter": "0,1,2,3",
339 "EventCode": "0xA3",
341 "PEBScounters": "0,1,2,3",
344 "UMask": "0xc"
349 "Counter": "0,1,2,3",
351 "EventCode": "0xa3",
353 "PEBScounters": "0,1,2,3",
356 "UMask": "0x5"
361 "Counter": "0,1,2,3,4,5,6,7",
363 "EventCode": "0xa3",
365 "PEBScounters": "0,1,2,3,4,5,6,7",
368 "UMask": "0x14"
373 "Counter": "0,1,2,3,4,5,6,7",
375 "EventCode": "0xa3",
377 "PEBScounters": "0,1,2,3,4,5,6,7",
380 "UMask": "0x4"
385 "Counter": "0,1,2,3,4,5,6,7",
386 "EventCode": "0xa6",
388 "PEBScounters": "0,1,2,3,4,5,6,7",
392 "UMask": "0x2"
397 "Counter": "0,1,2,3,4,5,6,7",
398 "EventCode": "0xa6",
400 "PEBScounters": "0,1,2,3,4,5,6,7",
404 "UMask": "0x4"
409 "Counter": "0,1,2,3,4,5,6,7",
410 "EventCode": "0xa6",
412 "PEBScounters": "0,1,2,3,4,5,6,7",
416 "UMask": "0x8"
421 "Counter": "0,1,2,3,4,5,6,7",
422 "EventCode": "0xa6",
424 "PEBScounters": "0,1,2,3,4,5,6,7",
428 "UMask": "0x10"
433 "Counter": "0,1,2,3,4,5,6,7",
435 "EventCode": "0xA6",
437 "PEBScounters": "0,1,2,3,4,5,6,7",
441 "UMask": "0x40"
446 "Counter": "0,1,2,3",
447 "EventCode": "0x87",
449 "PEBScounters": "0,1,2,3",
450 …0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the num…
453 "UMask": "0x1"
458 "Counter": "0,1,2,3",
459 "EventCode": "0x55",
461 "PEBScounters": "0,1,2,3",
465 "UMask": "0x1"
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
470 "Counter": "Fixed counter 0",
474 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
476 "UMask": "0x1"
479 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
481 "Counter": "0,1,2,3,4,5,6,7",
482 "EventCode": "0xc0",
485 "PEBScounters": "0,1,2,3,4,5,6,7",
486 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
492 "Counter": "0,1,2,3,4,5,6,7",
493 "EventCode": "0xc0",
496 "PEBScounters": "0,1,2,3,4,5,6,7",
498 "UMask": "0x2"
503 "Counter": "Fixed counter 0",
507 …R) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
509 "UMask": "0x1"
514 "Counter": "0,1,2,3,4,5,6,7",
516 "EventCode": "0xc0",
519 "PEBScounters": "0,1,2,3,4,5,6,7",
523 "UMask": "0x1"
526 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
528 "Counter": "0,1,2,3,4,5,6,7",
530 "EventCode": "0x0D",
532 "PEBScounters": "0,1,2,3,4,5,6,7",
533 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
536 "UMask": "0x3"
541 "Counter": "0,1,2,3,4,5,6,7",
542 "EventCode": "0x0d",
544 "PEBScounters": "0,1,2,3,4,5,6,7",
548 "UMask": "0x80"
553 "Counter": "0,1,2,3,4,5,6,7",
554 "EventCode": "0x0D",
556 "PEBScounters": "0,1,2,3,4,5,6,7",
560 "UMask": "0x1"
565 "Counter": "0,1,2,3,4,5,6,7",
566 "EventCode": "0x0d",
568 "PEBScounters": "0,1,2,3,4,5,6,7",
569 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
572 "UMask": "0x10"
577 "Counter": "0,1,2,3",
578 "EventCode": "0x03",
580 "PEBScounters": "0,1,2,3",
584 "UMask": "0x8"
589 "Counter": "0,1,2,3",
590 "EventCode": "0x03",
592 "PEBScounters": "0,1,2,3",
596 "UMask": "0x2"
601 "Counter": "0,1,2,3",
602 "EventCode": "0x07",
604 "PEBScounters": "0,1,2,3",
608 "UMask": "0x1"
613 "Counter": "0,1,2,3",
614 "EventCode": "0x4c",
616 "PEBScounters": "0,1,2,3",
617 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
620 "UMask": "0x1"
625 "Counter": "0,1,2,3",
627 "EventCode": "0xA8",
629 "PEBScounters": "0,1,2,3",
630 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
633 "UMask": "0x1"
638 "Counter": "0,1,2,3",
640 "EventCode": "0xa8",
642 "PEBScounters": "0,1,2,3",
643 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
646 "UMask": "0x1"
651 "Counter": "0,1,2,3",
652 "EventCode": "0xa8",
654 "PEBScounters": "0,1,2,3",
655 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
658 "UMask": "0x1"
663 "Counter": "0,1,2,3,4,5,6,7",
666 "EventCode": "0xc3",
668 "PEBScounters": "0,1,2,3,4,5,6,7",
672 "UMask": "0x1"
675 "BriefDescription": "Self-modifying code (SMC) detected.",
677 "Counter": "0,1,2,3,4,5,6,7",
678 "EventCode": "0xc3",
680 "PEBScounters": "0,1,2,3,4,5,6,7",
681 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
684 "UMask": "0x4"
689 "Counter": "0,1,2,3,4,5,6,7",
690 "EventCode": "0xcc",
692 "PEBScounters": "0,1,2,3,4,5,6,7",
695 "UMask": "0x20"
700 "Counter": "0,1,2,3,4,5,6,7",
701 "EventCode": "0xcc",
705 "UMask": "0x40"
710 "Counter": "0,1,2,3,4,5,6,7",
711 "EventCode": "0xa2",
713 "PEBScounters": "0,1,2,3,4,5,6,7",
714 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
717 "UMask": "0x8"
722 "Counter": "0,1,2,3,4,5,6,7",
723 "EventCode": "0xa2",
725 "PEBScounters": "0,1,2,3,4,5,6,7",
728 "UMask": "0x2"
733 "Counter": "0,1,2,3,4,5,6,7",
734 "EventCode": "0x5e",
736 "PEBScounters": "0,1,2,3,4,5,6,7",
737 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
740 "UMask": "0x1"
745 "Counter": "0,1,2,3,4,5,6,7",
748 "EventCode": "0x5E",
751 "PEBScounters": "0,1,2,3,4,5,6,7",
752 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
755 "UMask": "0x1"
758 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
760 "Counter": "0,1,2,3,4,5,6,7",
761 "EventCode": "0xa4",
763 "PEBScounters": "0,1,2,3,4,5,6,7",
764 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
767 "UMask": "0x2"
772 "Counter": "0,1,2,3,4,5,6,7",
773 "EventCode": "0xa4",
775 "PEBScounters": "0,1,2,3,4,5,6,7",
776 …t were issued but not retired from the specualtive path as well as the out-of-order engine recover…
779 "UMask": "0x8"
782 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
787 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
790 "UMask": "0x4"
793 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
795 "Counter": "0,1,2,3,4,5,6,7",
796 "EventCode": "0xa4",
798 "PEBScounters": "0,1,2,3,4,5,6,7",
799 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
802 "UMask": "0x1"
805 … "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
807 "Counter": "0,1,2,3",
808 "EventCode": "0x56",
810 "PEBScounters": "0,1,2,3",
811 "PublicDescription": "Uops exclusively fetched by decoder 0",
814 "UMask": "0x1"
817 "BriefDescription": "Number of uops executed on port 0",
819 "Counter": "0,1,2,3,4,5,6,7",
820 "EventCode": "0xa1",
822 "PEBScounters": "0,1,2,3,4,5,6,7",
823 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
826 "UMask": "0x1"
831 "Counter": "0,1,2,3,4,5,6,7",
832 "EventCode": "0xa1",
834 "PEBScounters": "0,1,2,3,4,5,6,7",
835 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
838 "UMask": "0x2"
843 "Counter": "0,1,2,3,4,5,6,7",
844 "EventCode": "0xa1",
846 "PEBScounters": "0,1,2,3,4,5,6,7",
847 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
850 "UMask": "0x4"
855 "Counter": "0,1,2,3,4,5,6,7",
856 "EventCode": "0xa1",
858 "PEBScounters": "0,1,2,3,4,5,6,7",
859 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
862 "UMask": "0x10"
867 "Counter": "0,1,2,3,4,5,6,7",
868 "EventCode": "0xa1",
870 "PEBScounters": "0,1,2,3,4,5,6,7",
871 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
874 "UMask": "0x20"
879 "Counter": "0,1,2,3,4,5,6,7",
880 "EventCode": "0xa1",
882 "PEBScounters": "0,1,2,3,4,5,6,7",
883 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
886 "UMask": "0x40"
889 "BriefDescription": "Number of uops executed on port 7 and 8",
891 "Counter": "0,1,2,3,4,5,6,7",
892 "EventCode": "0xa1",
894 "PEBScounters": "0,1,2,3,4,5,6,7",
895 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
898 "UMask": "0x80"
903 "Counter": "0,1,2,3,4,5,6,7",
904 "EventCode": "0xB1",
906 "PEBScounters": "0,1,2,3,4,5,6,7",
910 "UMask": "0x2"
913 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
915 "Counter": "0,1,2,3,4,5,6,7",
917 "EventCode": "0xB1",
919 "PEBScounters": "0,1,2,3,4,5,6,7",
920 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
923 "UMask": "0x2"
926 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
928 "Counter": "0,1,2,3,4,5,6,7",
930 "EventCode": "0xB1",
932 "PEBScounters": "0,1,2,3,4,5,6,7",
933 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
936 "UMask": "0x2"
939 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
941 "Counter": "0,1,2,3,4,5,6,7",
943 "EventCode": "0xB1",
945 "PEBScounters": "0,1,2,3,4,5,6,7",
946 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
949 "UMask": "0x2"
952 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
954 "Counter": "0,1,2,3,4,5,6,7",
956 "EventCode": "0xB1",
958 "PEBScounters": "0,1,2,3,4,5,6,7",
959 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
962 "UMask": "0x2"
965 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
967 "Counter": "0,1,2,3,4,5,6,7",
969 "EventCode": "0xb1",
971 "PEBScounters": "0,1,2,3,4,5,6,7",
972 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
975 "UMask": "0x1"
978 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
980 "Counter": "0,1,2,3,4,5,6,7",
982 "EventCode": "0xb1",
984 "PEBScounters": "0,1,2,3,4,5,6,7",
985 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
988 "UMask": "0x1"
991 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
993 "Counter": "0,1,2,3,4,5,6,7",
995 "EventCode": "0xb1",
997 "PEBScounters": "0,1,2,3,4,5,6,7",
998 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1001 "UMask": "0x1"
1004 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1006 "Counter": "0,1,2,3,4,5,6,7",
1008 "EventCode": "0xb1",
1010 "PEBScounters": "0,1,2,3,4,5,6,7",
1011 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1014 "UMask": "0x1"
1019 "Counter": "0,1,2,3,4,5,6,7",
1021 "EventCode": "0xB1",
1024 "PEBScounters": "0,1,2,3,4,5,6,7",
1028 "UMask": "0x1"
1031 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1033 "Counter": "0,1,2,3,4,5,6,7",
1034 "EventCode": "0xb1",
1036 "PEBScounters": "0,1,2,3,4,5,6,7",
1039 "UMask": "0x1"
1044 "Counter": "0,1,2,3,4,5,6,7",
1045 "EventCode": "0xB1",
1047 "PEBScounters": "0,1,2,3,4,5,6,7",
1051 "UMask": "0x10"
1056 "Counter": "0,1,2,3,4,5,6,7",
1057 "EventCode": "0x0e",
1059 "PEBScounters": "0,1,2,3,4,5,6,7",
1063 "UMask": "0x1"
1068 "Counter": "0,1,2,3,4,5,6,7",
1070 "EventCode": "0x0E",
1073 "PEBScounters": "0,1,2,3,4,5,6,7",
1077 "UMask": "0x1"
1080 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1082 "Counter": "0,1,2,3,4,5,6,7",
1083 "EventCode": "0x0e",
1085 "PEBScounters": "0,1,2,3,4,5,6,7",
1086 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1089 "UMask": "0x2"
1094 "Counter": "0,1,2,3,4,5,6,7",
1095 "EventCode": "0xc2",
1097 "PEBScounters": "0,1,2,3,4,5,6,7",
1100 "UMask": "0x2"
1105 "Counter": "0,1,2,3,4,5,6,7",
1107 "EventCode": "0xc2",
1110 "PEBScounters": "0,1,2,3,4,5,6,7",
1114 "UMask": "0x2"
1119 "Counter": "0,1,2,3,4,5,6,7",
1121 "EventCode": "0xc2",
1124 "PEBScounters": "0,1,2,3,4,5,6,7",
1127 "UMask": "0x2"