Lines Matching +full:3 +full:a
3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
5 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
17 "Counter": "0,1,2,3",
22 "PEBScounters": "0,1,2,3",
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
31 "Counter": "0,1,2,3",
34 "PEBScounters": "0,1,2,3",
35 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
43 "Counter": "0,1,2,3,4,5,6,7",
49 "PEBScounters": "0,1,2,3,4,5,6,7",
56 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
65 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
73 "Counter": "0,1,2,3,4,5,6,7",
79 "PEBScounters": "0,1,2,3,4,5,6,7",
88 "Counter": "0,1,2,3,4,5,6,7",
94 "PEBScounters": "0,1,2,3,4,5,6,7",
103 "Counter": "0,1,2,3,4,5,6,7",
109 "PEBScounters": "0,1,2,3,4,5,6,7",
118 "Counter": "0,1,2,3,4,5,6,7",
124 "PEBScounters": "0,1,2,3,4,5,6,7",
125 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
131 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
133 "Counter": "0,1,2,3,4,5,6,7",
139 "PEBScounters": "0,1,2,3,4,5,6,7",
140 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
146 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
148 "Counter": "0,1,2,3,4,5,6,7",
154 "PEBScounters": "0,1,2,3,4,5,6,7",
155 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
163 "Counter": "0,1,2,3,4,5,6,7",
169 "PEBScounters": "0,1,2,3,4,5,6,7",
170 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
176 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
178 "Counter": "0,1,2,3,4,5,6,7",
184 "PEBScounters": "0,1,2,3,4,5,6,7",
185 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
191 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
193 "Counter": "0,1,2,3,4,5,6,7",
199 "PEBScounters": "0,1,2,3,4,5,6,7",
200 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
206 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
208 "Counter": "0,1,2,3,4,5,6,7",
214 "PEBScounters": "0,1,2,3,4,5,6,7",
215 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
221 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
223 "Counter": "0,1,2,3,4,5,6,7",
229 "PEBScounters": "0,1,2,3,4,5,6,7",
230 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
236 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
238 "Counter": "0,1,2,3,4,5,6,7",
244 "PEBScounters": "0,1,2,3,4,5,6,7",
245 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
251 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
253 "Counter": "0,1,2,3,4,5,6,7",
259 "PEBScounters": "0,1,2,3,4,5,6,7",
260 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
266 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
268 "Counter": "0,1,2,3,4,5,6,7",
274 "PEBScounters": "0,1,2,3,4,5,6,7",
275 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
283 "Counter": "0,1,2,3,4,5,6,7",
289 "PEBScounters": "0,1,2,3,4,5,6,7",
296 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
298 "Counter": "0,1,2,3",
301 "PEBScounters": "0,1,2,3",
302 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
310 "Counter": "0,1,2,3",
313 "PEBScounters": "0,1,2,3",
322 "Counter": "0,1,2,3",
325 "PEBScounters": "0,1,2,3",
332 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
334 "Counter": "0,1,2,3",
337 "PEBScounters": "0,1,2,3",
338 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
346 "Counter": "0,1,2,3",
350 "PEBScounters": "0,1,2,3",
359 "Counter": "0,1,2,3",
363 "PEBScounters": "0,1,2,3",
372 "Counter": "0,1,2,3",
375 "PEBScounters": "0,1,2,3",
384 "Counter": "0,1,2,3",
388 "PEBScounters": "0,1,2,3",
397 "Counter": "0,1,2,3",
401 "PEBScounters": "0,1,2,3",
410 "Counter": "0,1,2,3",
413 "PEBScounters": "0,1,2,3",
422 "Counter": "0,1,2,3",
426 "PEBScounters": "0,1,2,3",
435 "Counter": "0,1,2,3",
440 "PEBScounters": "0,1,2,3",
449 "Counter": "0,1,2,3",
452 "PEBScounters": "0,1,2,3",
461 "Counter": "0,1,2,3,4,5,6,7",
464 "PEBScounters": "0,1,2,3,4,5,6,7",
465 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
473 "Counter": "0,1,2,3,4,5,6,7",
477 "PEBScounters": "0,1,2,3,4,5,6,7",
478 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
486 "Counter": "0,1,2,3,4,5,6,7",
491 "PEBScounters": "0,1,2,3,4,5,6,7",
492 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",