Lines Matching +full:per +full:- +full:cpu
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
15 …etric represents fraction of slots the CPU was stalled due to Frontend latency issues. For exampl…
19 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruct…
26 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruct…
30 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruc…
34 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
38 …CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching o…
42 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches…
46 …ion of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-c…
50 …"BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chang…
54 …"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chan…
58 …"BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to …
62 …CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used ins…
66 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
70 …"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend…
74 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …les in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pi…
82 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
83 "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
86 …"PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limit…
91 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /…
94 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
98 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Mis…
102 …CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an…
106 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Cl…
107 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
110 …CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the …
115 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
118 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
123 …cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@…
126 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
130 …"BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the…
131 …"MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVI…
134 …CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shor…
142 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
150 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
154 …"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses…
158 …"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misse…
162 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
166 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
174 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
179 … "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / CLKS",
186 …"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses …
187 … "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS",
190 …"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses…
194 …"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to …
198 …"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to…
210 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
214 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
226 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
230 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
234 …"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external m…
235 …"MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_U…
238 …"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external …
243 …"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\…
246 …-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests …
251 …CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
270 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
278 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
282 …n": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store …
286 …CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request be…
290 …"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store mis…
291 …etricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
294 …CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performa…
298 …"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due…
302 …CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; …
310 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
314 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
318 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
322 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
323 "MetricExpr": "tma_backend_bound - tma_memory_bound",
326 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
338 … estimates fraction of cycles the CPU performance was potentially limited due to Core computation …
339 …cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@…
342 …CPU performance was potentially limited due to Core computation issues (non divider-related). Two…
346 …"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any executi…
347 …ricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.T…
350 …action of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, P…
354 …ption": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle…
355 …xpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on …
358 …CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, …
362 …iefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle…
363 …xpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on …
366 …CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL,…
370 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
371 …"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\…
377 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
384 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
391 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
398 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
405 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
412 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
413 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
419 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads …
426 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads …
433 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
440 …on": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Stor…
447 …his metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simpl…
458 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
462 …raction of slots where the CPU was retiring light-weight operations -- instructions that require n…
463 "MetricExpr": "tma_retiring - tma_heavy_operations",
466 …CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-…
478 …": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations --…
482 …ots where the CPU was retiring heavy-weight operations -- instructions that require two or more uo…
486 …"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by…
490 …"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched b…
494 …"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the…
498 …CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long seq…
502 …"BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from…
503 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
506 …CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instr…
510 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
516 "BriefDescription": "Uops Per Instruction",
522 "BriefDescription": "Instruction per taken branch",
528 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
534 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
540 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
546 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
552 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
553 …cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if …
564 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
570 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
576 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
582 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
588 "BriefDescription": "Instruction per taken branch",
594 "BriefDescription": "Branch instructions per taken branch. ",
607 "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
618 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
624 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
630 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
636 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
642 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
648 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
661 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
667 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
673 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
679 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
685 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
691 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
697 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
703 "BriefDescription": "Average CPU Utilization",
722 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SM…
733 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
763 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
769 "BriefDescription": "C3 residency percent per core",
770 "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
775 "BriefDescription": "C6 residency percent per core",
776 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
781 "BriefDescription": "C7 residency percent per core",
782 "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
787 "BriefDescription": "C2 residency percent per package",
788 "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
793 "BriefDescription": "C3 residency percent per package",
794 "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
799 "BriefDescription": "C6 residency percent per package",
800 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
805 "BriefDescription": "C7 residency percent per package",
806 "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
811 "BriefDescription": "Uncore frequency per die [GHZ]",
817 "BriefDescription": "CPU operating frequency (in GHz)",
971 …of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
978 …dth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
992 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
1007 …"MetricExpr": "100 * ( UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS ) / UOPS_ISSUE…