Lines Matching +full:front +full:- +full:end

3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
8         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
31 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
40 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
170 …s event counts cycles during which the microcode sequencer assisted the Front-end in delivering uo…
232 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the…
243 …Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalle…
255 …Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of…
283         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
294         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",